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To: Dave B who wrote (36784)	1/27/2000 6:06:00 PM
From: denni	Respond to of 93625

>>p.s. denni, did you tell me you would be at the lunch? If so, I apologize -- I didn't include your name in recent messages I posted. will i be at lunch? maybe; just let me know where? i would be coming from socal. i'll let you know for sure later. make sure stuart knows where. i'm sure he would like to be there.

To: Dave B who wrote (36784)	1/27/2000 8:20:00 PM
From: Jdaasoc	Read Replies (1) \| Respond to of 93625

Dave: Flaming bag of dog crap next to support DDR. semibiznews.com Transmeta's Crusoe processor supports DDR memories without chip sets By Jack Robertson Semiconductor Business News (01/27/00, 01:03:52 PM EDT) SAN JOSE--Transmeta Corp.'s Crusoe microprocessor can use double data rate SDRAMs right away without waiting for a separate DDR chip set to be introduced on the market, according to company officials at the Platform 2000 Conference here. The Crusoe processor contains a memory controller supporting both the single data rate SDRAM or the DDR memories, said Daniel McKenna, director of technical marketing at Transmeta, which introduced the x86-compatible MPU last week (see Jan. 19 story). Transmeta officials based in nearby Saratoga said they believed DDR's lower 2.5-volt power supply will be an attractive feature for mobile PCs and handheld Internet devices, which is a targeted segment for the new microprocessor. The immediate ability of Crusoe to use DDR memory without waiting on a separate chip set could help push the higher speed memory in the market earlier, speculated McKenna. Other chip makers at the Platform Conference said the ramp of Crusoe into volume applications will play a role in whether or not the processor has much of an impact on DDR's growth. However, many of these companies seemed delighted that another microprocessor platform was using DDR. McKenna said Crusoe also has faster memory access speed that conventional chip sets because many of the controller functions -- especially register setup and timing -- is performed in software rather than hardware. "Just as Crusoe implements the microprocessor instruction set in software for faster operation, it also speed up memory considerably through software as well," he claimed. The integrated memory controller eliminates two clock cycles needed for separate chip sets. "The on-chip controller also eliminates delays when the processor must access memory through a separate chip set," McKenna added. Rivals are also developing MPUs with on-chip memory controllers for low-cost computer, which are expected to be introduced later this year. Intel Corp. has said its offering--called Timna--will be unveiled in the third quarter. Original plans call for Timna to support Direct Rambus DRAMs, but sources said a SDRAM version is being considered as well. Taiwan's VIA Technologies Inc. is also planning to bring out an integrated MPU with memory controller which will support SDRAMs