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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (90341)	1/28/2000 9:08:00 PM
From: milo_morai	Read Replies (1) \| Respond to of 1571401

Lots more GTW and AMD Athlon ad's getting TV coverage today. tveyes.com tveyes.com tveyes.com tveyes.com tveyes.com tveyes.com

To: Ali Chen who wrote (90341)	1/29/2000 3:12:00 AM
From: THE WATSONYOUTH	Read Replies (1) \| Respond to of 1571401

Re: "After all, why it should be a surprise? For example, the Cumine on-chip L2 cache is running physically at 1/2 core speed. Of course, Intel markedroids prefer not to overemphasize this fact." Actually, I think it was clever to do what they did. I will guess that the original Coppermine delay was the result of initially trying to the run the cache at full core speed. Logic devices are generally several microns in width. The SRAM devices are generally less than 1/2 micron in width. Often, the narrow device characteristics (Ion/Ioff/Vtlin/Vtsat/etc.) do not scale as they should with width(for a number of reasons.) Intel might have not been able to yield the SRAM at the highest frequencies because of this "narrow width effect" and thus adopted the 1/2 core speed/wide bus approach. They could then raise the Vt of the array devices to improve yield at the shortest channel lengths without compromising performance. Seems like a practical solution to me. I wouldn't doubt if AMD uses the same approach. THE WATSONYOUTH