To: Derek C. who wrote (9010 ) 1/31/2000 4:34:00 PM From: Binx Bolling Read Replies (1) | Respond to of 60323
Is the following Flash Technology relevant to Data Storage or is it only relevant to Code Storage? Philips Semiconductors Creates First Cost Effective, Embedded Flash Memory Process for 0.18 Micron CMOS Two Transistor Design for Flash Memory Offers Reduced Current Consumption Updated 8:23 AM ET January 25, 2000 SUNNYVALE, Calif. (BUSINESS WIRE) - Philips Semiconductors, an affiliate of Royal Philips Electronics (NYSE:PHG), today announced the design of an embedded Flash memory process for its 0.18 micron CMOS process. The design uses a two transistor cell with stacked gates that offers many advantages over traditional, one transistor Flash memory designs, such as easier and faster testing, more efficient programming and less current consumption without significantly increasing the overall silicon area. "I believe that we are the first company to have created cost effective, embedded Flash memory for 0.18 micron CMOS," explained Theo Claasen, Philips Semiconductors chief technology officer. "The ability to embed memory is a vital part of Philips Semiconductors' Nexperia(TM) Silicon System Platforms strategy for creating complete products on a single chip. "It offers cost advantages because the memory size can be precisely tailored to suit the application rather than having to use off-the-shelf memory sizes. We have developed a two transistor cell design that has been optimized to provide the benefits of this approach without the drawbacks of increasing the overall size of the memory module when compared to the traditional one transistor cell." Philips Semiconductors' two-transistor (2T) Flash memory cell occupies slightly more silicon than a typical one-transistor (1T) cell (0.78 square microns for Philips Semiconductors' 2T cell compared to 0.5 square microns for a typical 1T cell). However, the overall area of a Philips Semiconductors CMOS18 Flash memory module is similar in size to a module implemented using 1T cells because the 2T design requires considerably less peripheral circuitry for programming and erasure. For example, 1T cells normally employ a "hot channel electron" programming technique that requires a powerful charge pump capable of delivering several milliamps at a voltage of around 12V. Philips Semiconductors' CMOS18 Flash utilizes the Fowler-Nordheim tunnelling to program and erase the memory cells, requiring a much smaller charge pump that only delivers microamps. Efficient design of peripheral circuitry for memory control and testing further reduces the overall size of the 2T module to achieve silicon area parity with 1T designs. Extensive use of parallel programming also makes testing considerably faster, which is a significant factor in the production cost of the chip. For example, a 16 MB Philips Semiconductors' CMOS18 Flash memory module can be tested in 10 to 20 seconds, compared to a range of 80 to 140 seconds for a 16MB memory implemented with 1T cells. By separating the memory transistor from the selection transistor, Philips Semiconductors' 2T design also overcomes the over-erase and Vt spread (MOSFET threshold voltage variation) problems that are typical of 1T designs. About Philips Semiconductors Philips Semiconductors is the eighth largest semiconductor supplier in the world according to Dataquest's 1998 market share report. Philips Semiconductors' innovations in digital audio, video and mobile technology place the company in a leadership position in the consumer, multimedia and wireless communications markets. As a global company, offices in 40 countries serve major markets. Philips Semiconductors, headquartered in Eindhoven, The Netherlands, is an affiliate of Royal Philips Electronics. Please join us at the Philips Semiconductors website (www.semiconductors.philips.com) for further information. Contact: Philips Semiconductors Paul Morrison, 408/474-5065 paul.morrison@vlsi.com or Porter Novelli Convergence Group Gennis Lafayette, 415/975-2298 gennis.lafayette@pnicg.com