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To: Tony Viola who wrote (97959)	1/31/2000 8:06:00 PM
From: Paul Engel	Respond to of 186894

Tony - Re: "How they do that? Use each edge to get 200 and then Manchester encode to get 400? Not. We'll have to wait and see." I will wait with you to see ! Paul

To: Tony Viola who wrote (97959)	1/31/2000 8:24:00 PM
From: Elmer	Read Replies (1) \| Respond to of 186894

Re: "How they do that? Use each edge to get 200 and then Manchester encode to get 400? Not. We'll have to wait and see." If you look at the AGP2 bus, which is also "quad pumped" you will see that the source synchronous (SS) clock is running at 2x the bus rate, i.e. 133MHz vrs 66MHz basic bus rate. Double pumping the 133MHz SS Clock gives you 266MHz data rate or 4x the basic clock rate. What really sets me back on my heels is the 128 bit bus for McKinley. that's 16 bytes @400MHz or 6.4GBPS bandwidth for a processor that will already have a reported 3 levels of caching!!! Yikes!!!! EP