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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Paul Engel who wrote (98492)	2/8/2000 3:16:00 AM
From: Paul Engel	Read Replies (2) \| Respond to of 186894

Intel Investors - More details of ITanium from Gadi Singer's presentation at ISSCC. Unfortunately, these "details" are buried at the end of an article about IBM's 4.5 GHz whatchamakallit. Note - the 460GX memory size - exactly as Tenchsatsu already told us (Thank you, Ten !). "Other Itanium details: The 460GX chip set supports four processors and up to 65GB of SDRAM; the backside bus has a data-transfer rate of 12.8GB per second; the front-side bus has bandwidth of 2.1GB per second; and the floating point can do more than 1,000 decrypts per second, or up to 10 times that of other 64-bit RISC chips, Singer said. Intel also said the L3 cache runs at core processor frequencies. Intel officials said four other IA-64 processors are in the works besides Itanium, code-named McKinley, Madison, Deerfield and one whose name was not released. " Paul [==============================} IBM shows design for super-fast chip By Ken Popovich, PC Week February 7, 2000 11:15 AM PT URL: zdnet.com IBM unveiled a new computer circuit design today that researchers say will enable chips built using conventional silicon transistors to reach speeds of up to 4.5GHz. The design, called "Interlocked Pipeline CMOS," could also reduce power consumption by 50 percent compared to today's standard high-performance chips, researchers said. IBM representatives will offer further details on the design and its eventual implementation at the International Solid-State Circuits Conference this week in San Francisco. The key to the IPCMOS design is a distributed "clock" function -- the clock basically synchronizes the actions of the circuits. Today's chips use a centralized clock to synchronize operations of an entire chip, ensuring that all operations run at the same interval, or cycle. The clock waits for all the operations on a chip to finish before starting the next cycle, with the speed of the entire chip limited to the pace of the slowest operation. In the new design the clock is decentralized, and locally generated clocks run smaller sections of circuits. Switching to locally generated clocks allows faster sections of circuits to run at higher cycles since they don't have to wait for slower operations to catch up. Decentralized clocks also reduce total power consumption, IBM researchers said, by eliminating the need to send the clock signal across the entire chip. "Maintaining a synchronous clock across an entire chip becomes increasingly difficult as performance rises, and the clock itself can limit performance," said Stanley Schuster, one of the researchers working on IPCMOS. "We believe this new design will help us overcome those problems in future generations of high-speed chips." More sneak peeks The IPCMOS design is one of 14 research papers IBM is presenting at the San Francisco conference. Among the other technological advances being presented by IBM are: -- a high-frequency, short-pipeline processor that uses copper interconnects, a unique circuit design, and dynamic programmable logic arrays to achieve frequencies of 1GHz or more using existing production technology with a short-pipeline architecture. -- a demonstration of a copper-based, embedded DRAM design with density comparable to DRAM and speed comparable to the fastest SRAM. The design could be used in future GHz system-on-a-chip products and would provide a data-transfer rate of 1 terabit per second. -- a prototype micromechanical device called "millipede" for high-density storage that would use an array of 1,000 tiny cantilevers to read and write data, potentially enabling storage densities of more than 400 billion bits per square inch. Intel at the show Intel Corp. officials were also on hand at the show Monday, fleshing out their IA-64 plans. They said the first 64-bit Itanium chip, due in the second half, will come in at 800MHz, or slower than what 32-bit Pentium IIIs will be capable of at the time. Officials said the Itanium uses memory technology designed by Intel but were otherwise unforthcoming about it. "We don't see memory as a limiter," said Gadi Singer, vice president and general manager of Intel's IA-64 processor division. "Both in terms of capacity and performance, this is not a limit." Other Itanium details: The 460GX chip set supports four processors and up to 65GB of SDRAM; the backside bus has a data-transfer rate of 12.8GB per second; the front-side bus has bandwidth of 2.1GB per second; and the floating point can do more than 1,000 decrypts per second, or up to 10 times that of other 64-bit RISC chips, Singer said. Intel also said the L3 cache runs at core processor frequencies. Intel officials said four other IA-64 processors are in the works besides Itanium, code-named McKinley, Madison, Deerfield and one whose name was not released. Additional reporting by Anne Knowles