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To: Tenchusatsu who wrote (98528)2/8/2000 2:10:00 PM
From: Paul Engel  Read Replies (2) | Respond to of 186894
 
Ten - Re: "that's 128 bits wide, twice the width of Xeon's BSB. Along with a size of 4 MB, that's going to be one monster L3 cache."

Those SRAM "test chips" will come in handy when used as this L3 cache.

My calculations are that 4 MegaBytes of SRAM cache require 201 MILLION TRANSISTORS !

Just the bond pads/C4 bumps must eat up a lot of real estate on these chips - Merced PLUS the L3 cache chips.

Paul