Switch fabrics: advantages, limitations
By Sean Long, Director of Marketing, I-Cube Inc., Campbell, Calif., EE Times
Sep 21, 1999 (8:34 AM)
URL: eetimes.com
Communication system designers must satisfy the never-ending demand for more bandwidth and features to satisfy changing market requirements. The key to meeting those challenges is the designer's ability to get the most out of the chip interconnects that constitute the foundation of a system's switching architecture.
Although switching theory has been researched for years, new VLSI silicon technology allows engineers to implement those theories in standard products rather than ASIC devices. The use of reconfigurable switches allows them to tailor the performance of their designs, accommodate a wide variety of designs and features and more easily meet evolving industry standards.
Designers have traditionally based their systems on three basic interconnect architectures: shared bus, also known as multidrop; ring interconnect, using point-to-point architecture; and the crossbar switch. Shared-bus architectures are easy to understand and can be constructed from widely available standard products for PCI, VME or other bus architectures.
However, despite those advantages design engineers find that shared-bus architectures have practical performance limits. They suffer from the bandwidth limitation of one data transfer at a time and the inability to scale cost-effectively with higher clock rates and data paths.
Ring architectures overcome the limited data-transfer rates of shared buses by using concurrent data transfers to achieve higher aggregate bandwidths. But ring architectures are saddled with high latency during data transfers, lack cost-effective components and have reliability problems such as single points-of-failure.
Given the limitations of the first two interconnect architectures, designers have long examined the use of crossbar switches, a concept that comes from the electromechanical assemblies first used in telephone switching offices in the early 1900s. Essentially, a crossbar switch network is constructed from crosspoint switches that form a crosspoint-switching matrix. Closing the switch at the appropriate crosspoint in the matrix creates a connection between an input and an output.
The idea of constructing large switch networks from smaller ones is fundamental to the theory of switching architectures. But there is a basic limitation to building larger crosspoint switch networks. When the switch fabric is doubled, it requires four times as many chips. For example, scaling a 32-input x 32-output switch up to 64 x 64 requires four 32-input x 32-output switches. The methodology becomes very expensive and unwieldy as more and more devices are needed to build a larger switch network. Today's larger crossbar switches, however, overcome that limitation.
Crosspoint switches offer several other design benefits. High-performance crossbar switches are nonblocking, erasing the bandwidth limitations of one-at-a-time connections, and they have the flexibility of connecting any input to any output. In addition to its basic architectural advantages, the crossbar switch can be implemented in ASICs, FPGAs or crossbar chips.
Further, the best solutions let the designer configure the device's switch matrix, input/output buffers and control registers to simplify the design of switching matrices for many types of communication systems.
Add-drop multiplexers and digital cross-connect systems are two good examples of systems that benefit from reconfigurable crosspoint switch architectures. Those network elements implement synchronous optical network (Sonet) and synchronous digital hierarchy (SDH) standards, which specify a range of optical interface transmission rates. To fully implement those standards, a system family must cover several different data rates and configurations.
Sonet and SDH multiplexers are specified by speed, such as OC-3 (STM-1), and are capable of adding or dropping signals onto a Sonet link. An add/drop mux typically includes both high-speed (OC-n) and low-speed (e.g., DS1, DS3, STS-1, OC-1) interface cards and a switching matrix. The interface cards interface lines and process signals as well as handle the interface to the switch matrix. All of the traffic passes through the matrix, and connections are reconfigured as add/drop, terminal or repeater.
Plenty of I/Os
A digital cross-connect (DCC) system is a digital-switching matrix used to switch and rearrange signals, thereby setting up relatively permanent connections between input and output signals. DCCs need a large number of I/Os.
The lack of standard products for telecom equipment such as add/drop multiplexers or DCCs has resulted in most switch matrices' being implemented using custom integrated circuits. The availability of high-port-count reconfigurable switches as standard components will give engineers new options for building the equipment that makes up the communications infrastructure. Reconfigurable crossbar switches can help designers quickly design a switch matrix that can handle a number of data rates and configuration options.
Crossbar-switching arrays can be designed two ways. The first uses an N-way multiplexer at each output port to select data from the input ports. This is the traditional way semiconductor vendors have built crossbar switch products and while it is easy to understand, it is limited in terms of architectural flexibility and performance and it is difficult to implement efficiently in silicon.
The second uses a crosspoint array, which has a switching element at each input/output intersection. Basically, this method offers a high-density crosspoint array, which offers greater flexibility than traditional crossbar switches, making it feasible to build large switches in a cost-effective way using modern CMOS technology.
Engineers have three alternatives for implementing a crossbar switch fabric: FPGAs, ASICs and application-specific standard product (ASSP) crosspoint switches.
FPGAs are available from a number of suppliers, have a large user base and design engineers are familiar with FPGA products and design tools. For applications with a limited number of ports and lower data rates, FPGAs offer a good solution with the additional advantage of allowing engineers to integrate other functionality into the "switch."
However, FPGAs are a poor architectural match for complex switching applications that require high port counts or higher data rates. Because FPGAs use the N-way multiplexer approach to implementing a crosspoint switch, making it more difficult to implement wide and fast muxes, they are a poor option for high-port-count switches. Additionally, these designs require high routing density, which results in poor performance and logic utilization, making FPGAs unsuitable for applications with higher port counts or data rates.
ASICs have the potential to offer a complete system-on-chip solution. But ASICs require an investment in additional engineering resources, design tools and libraries, as well as upfront nonrecurring engineering (NRE) charges. Because it is difficult to modify an ASIC design once it is completed, the time-to-market is longer and the risks are higher. Additionally, ASIC designs restrict the designer's ability to reuse them in future projects.
The digital crosspoint switch (DCS) is a new category of ASSP that use a 100 percent nonblocking switch matrix. This means that any I/O port can be connected to any other I/O port, regardless of other connections in the switch. DCS devices support large I/O switch arrays as well as the high system clock rates needed for the design of high-speed communication systems. Predictable and deterministic timing, bidirectional switch routing and programmable I/Os simplify the design process. Moreover, DCS devices are reconfigurable and in-system programmable, simplifying initial design efforts and changes or upgrades after system manufacture.
One example of a digital crosspoint family is I-Cube's DCS products. The architecture consists of four basic blocks: switch matrix, programmable I/O, configuration and switch control, and clocking and tristate controls (port control signals).
The DCS products use a dedicated pass transistor and associated programming SRAM cell for all possible pairs of I/O ports. The switch matrix lines are constructed using a two-dimensional wiring structure where the horizontal and vertical lines are permanently connected at the diagonal points.
The switch matrix structure has several attributes, particularly fast propagation delays that are totally predictable. Propagation delays between pin pairs are closely matched and have very little skew, providing a deterministic architecture and making control software fast and simple. Each programmable I/O port on the switching device is connected to a unique line in the switch matrix. Digital signals are brought into the device through I/O ports that are configured as inputs. The signals are switched using the switch matrix and go out over the I/O ports that are configured as outputs. A parallel interface for fast reconfiguration of the switch matrix and I/O ports is available. |
