Preview of 2/22 Texas Instrument Major DSP annoucement:
Lucent, TI prep high-performance DSPs
By Peter Clarke and Rick Merritt
EE Times
(02/09/00, 05:09:58 PM EDT)
SAN FRANCISCO ? Aiming at the burgeoning market for communications gear, Lucent Technologies and Texas Instruments Inc. will roll plans for competing digital signal processing architectures in the next several weeks that could reshape the landscape for high-performance DSPs.
Lucent plans to roll out before April a system-on-chip platform under the name Daytona that enables what the company believes will be a new capability to readily create powerful custom one-chip multiprocessing devices. The Daytona platform ? which uses a cache coherent, split-transaction on-chip bus ? will be the first major vehicle for the company's Starcore DSP, which it co-developed with Motorola Inc.
Separately, on February 22, Texas Instruments will attempt to reclaim its technology leadership in DSP by announcing a new core that sources said will set a new watermark in performance and low-power operation. The core will be based on a new approach to very long instruction word (VLIW) techniques. TI is only expected to announce the core and not to discuss any specific plans for putting the core into a standard product or system-on-chip offering.
The TI core will sport high performance and low power figures "never seen before" based on a "new look at VLIW," said a source close to the company. TI declined to comment on its plans prior to the formal launch.
For its part, Lucent provided deep insights into its Daytona DSP at the International Solid State Circuits Conference here, where Bell Labs detailed research on a multiprocessing media processor that was the basis for the commercial system-chip offering.
Joseph Williams, member of the technical staff at Bell Labs, described a working signal processor based on four processor elements linked on a 32-bit address, 128-bit data split-transaction on-chip bus that is at the heart of the Daytona architecture.
"This DSP is the first implementation of this [Daytona] platform," said Williams, who has been working on the project for three years. "Our [new] architecture methodology and software to build a system-on-chip started with this chip."
Lucent's approach is different from the SoC offerings of other vendors such as Motorola and IBM, because the Lucent on-chip bus is cache coherent and is thus capable of handling an on-chip symmetric multiprocessing design, Williams said. A key to the Lucent plan is that the company will deliver software that it claims will ease the path to turning applications written for a single processor into code that leverages multiple processing elements chosen by the designer.
Minimal effort
"The amount of effort to schedule multiple processors is minimal," said Williams. "Programmers can focus mainly on writing for a single processor. Time-to-market is so important that we have focused the architecture on this."
Williams said a past attempt from Texas Instruments in multiprocessing DSPs, with a four-way C80 using a crossbar switch, was largely unsuccessful because programmers had to explicitly schedule processor tasks ? a time consuming chore ? and the system lacked cache coherence.
The cache coherence in Daytona insures that designs will conform to known latency limits and stay within the needs of a real-time task. The bus uses a cache locking scheme, so any off-processor memory access delay is fixed. It also employs a non- blocking DMA function distributed through the system-chip. In addition, Lucent developed its own real-time kernel as well as a library of low-level system calls in C as part of the Daytona software.
Williams said Daytona was not limited to a homogeneous architecture where identical resources are repeated in the chip. "This is intended as a platform for rapid prototyping of communications applications," he said. "You could include a DSP optimized for wireless applications, a DSP optimized for wireline applications, a RISC microprocessor, a microcontroller and even dedicated hardware acceleration of particular tasks. In development you can play around with the resources before deciding on the final optimized design that would reuse the appropriate number of processing elements. It promotes design reuse."
Williams disclosed that work has begun on a 32-processor, second-generation Daytona chip intended to push the bounds of performance. With eight times the resources and a 200-MHz clock, the implementation should yield 25.6 billion multiply-accumulate (MAC) operations per second, or 16 times the performance of the first-generation Daytona at three to four times the power consumption, Williams said.
Telecom target
Both the upcoming TI core and the Lucent Daytona platform are targeting the rapidly growing market for back-end communications systems, such as remote access modem pools at Internet service providers, digital subscriber line gear in a telco central office or next-generation cellular basestations. In all these applications, high performance and low power are critical.
"People are asking, 'What's your power consumption per port and your die size in millimeters per port and how may ports on your DSP?,' " said Will Strauss, president of market watcher Forward Concepts (Tempe, Ariz.). "That's why you need more powerful DSPs."
Strauss singled out two high-growth applications as particular targets for the new chips. The market for voice-over-Internet-Protocol (VoIP) gateways will grow 300 percent this year, he said. About 5.6 million VoIP ports shipped last year, up from 1.2 million in 1998. "Cisco is the 800 pound gorilla here," he said. In addition, third-generation cellular basestations are expected to require 600-800 Mips of processing power, up from 100 Mips for today's systems.
With the Daytona SoC platform Lucent is "targeting the entire communications space from wireless to wired on up to switching," said Williams.
"We are aiming at the high-performance system-on-chip space and we will deliver the pieces to bring that all together with a great deal of capabilities for communications," said Mark Pinto, chief technology officer and vice president of platform technology in Lucent's microelectronics group.
Pinto mentioned the Daytona research chip in a keynote speech at ISSCC. After his talk he said Lucent would roll out by April a commercial offering based on the technology.
"This fits into Lucent's overall strategy of wanting to have a powerful ASIC methodology," said Strauss. However, he said IBM already has a foothold on this market with its own system-chip strategy.
And both companies face two more architectures yet to come to market this year ? the TigerSharc from Analog Devices Inc., and a new DSP architecture being co-developed by ADI and Intel Corp. The latter architecture is expected to be formally announced by June.
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