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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Process Boy who wrote (93443)	2/16/2000 1:00:00 AM
From: semiconeng	Read Replies (2) \| Respond to of 1571016

This is absolutely not true. The product was plain vanilla .18 production process. If it was a CD skew wafer or not, I don't know, but that is certainly possible. And as far as I know no special cooling methods employed. PB A CD Skew Huh? That's one that I hadn't thought of. Wouldn't it be difficult to skew all the layers, or do you think that it was just "Poly Layer"? Or are you just saying that they ran an FE Wafer, and set the Focus/Exposure of the Stepper accordingly? I know when we do it, it's a big pain in the butt to maintain the desired CD's.... SemiConEng

To: Process Boy who wrote (93443)	2/16/2000 1:06:00 AM
From: kapkan4u	Read Replies (1) \| Respond to of 1571016

<This is absolutely not true. The product was plain vanilla .18 production process. If it was a CD skew wafer or not, I don't know, but that is certainly possible. And as far as I know no special cooling methods employed> What else should I expect from the Intel "official" SI moderator? The truth is that you have no foggiest idea, beyond the Intel press releases. Last time when I asked you about different clock domains in the Willamette core, you had no clue, until Elmer PMed you. After that you pretended that you knew all along what I was talking about. Kap

To: Process Boy who wrote (93443)	2/16/2000 9:05:00 AM
From: Dan3	Read Replies (1) \| Respond to of 1571016

Re: The product was plain vanilla .18 production process (Willamette demo) If that's the case, it was an impressive part. I'm not sure a 20 stage pipe is such a great idea, but I'll leave that discussion to those who know more about it. (I thought that pipeline optimal length was generally considered to be around 10). Can simple instructions like inc be retired in fewer clocks? Is 20 clocks really the exception rather than the rule? Dan