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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (94163)	2/18/2000 11:12:00 PM
From: Process Boy	Read Replies (1) \| Respond to of 1570881

Ten and Thread - Article about Willy FSB licensing. eet.com Intel will strictly control 400-MHz bus By Will Wade and Rick Merritt EE Times (02/18/00, 3:56 p.m. EST) PALM SPRINGS, Calif. ? Willamette, the 32-bit Pentium processor announced by Intel Corp. at this week's Intel Developer Forum, sports a processor bus that raises a new batch of intellectual property issues for engineers looking to build core logic for Intel's CPUs. Willamette uses a 400-MHz front-side bus that seems in some significant respects to be a fresh design over the existing P6 bus of the Pentium III line. Intel said it will exercise control over the use of the Willamette processor bus, and a company with rights to the current P6 bus will not have rights to build chips for Willamette, said Paul Otellini, general manager of the architecture business group of Intel. Otellini would not say whether Intel has licensed or would license OEMs or third parties to use the Willamette bus, which offers throughput up to 3.2 Gbytes/second. "I'm not going to talk about that," Otellini said. "OEMs know our plans and our strategies." Via Technologies Inc. (Taipei, Taiwan), one of the handful of third-party PC chip set makers, has no current plans to offer core logic that supports Willamette. But Donald Eubank, marketing specialist at the company's U.S. offices in Fremont, Calif., said the company would likely pursue such a design if Willamette becomes a high-volume mainstream product. Via is currently locked in a licensing dispute with Intel over Via's Apollo Pro133A chip set, which supports 133-MHz bus speeds. Intel claims Via is not permitted to use the bus under an agreement signed by the companies. Intel revoked Via's license to produce chip sets for the P6 bus architecture last summer, but Via sidestepped the issue by having the chip sets manufactured by National Semiconductor Corp., which has a separate cross-licensing agreement with Intel. At Intel's request, the U.S. International Trade Commission is investigating Via and other Taiwan chip makers for unfair trade practices. Slim chance Eubank said Intel is unlikely to grant Via a new bus license at this point, but said that Willamette will need to be compatible with existing bus designs if Intel wants it to quickly move into the mainstream. If that is the case, Via will be able to continue shipping chip sets for both the current generation of processors and Willamette-class chips, Eubank said. Raju Vegesna, chief executive officer of ServerWorks Inc. (Santa Clara, Calif.), would not comment on any licensing negotiations between his company and Intel. ServerWorks, formerly known as Reliance Computer Corp., makes a range of high-end chip sets for Pentium-class processors. Other chip set makers include Acer Laboratories (Taipei) and Silicon Integrated Systems Corp. (Hsinchu, Taiwan). The fast Willamette bus also throws a new wrinkle into the performance race between Intel and Advanced Micro Devices Inc. (AMD). AMD (Sunnyvale, Calif.) currently uses a 200-MHz processor bus originally designed to support the Alpha microprocessor architecture and licensed to AMD by Compaq Computer Corp. That bus design, the EV6, can scale to speeds of 400 MHz, and AMD plans to introduce a chip set in the second half of this year, called the 760, that will allow AMD's Athlon processors to utilize front-side bus speeds of 266 MHz. The 760 chip set will also support 233-MHz Double-Data-Rate DRAM technology. AMD has no current plans to introduce chip sets that support faster bus speeds, or to license a successor to the EV6 bus that will take AMD beyond those speeds.

To: Tenchusatsu who wrote (94163)	2/19/2000 1:09:00 AM
From: Scumbria	Read Replies (1) \| Respond to of 1570881

Ten, So it seems Intel went all out to build a processor around a very long pipeline. As I pointed out before, it does seem like Intel is betting everything on clock speed. It is nonsensical these days to do anything else other than a deep pipeline. The only way to achieve high clock speed is through a balanced, deep pipeline. Intel's management deserves credit for allowing the building of a 20 stage pipe. It is too bad that the Athlon pipeline is not longer, because it will have a hard time keeping up with Willy. There are also "hazards" in a program's code which causes "pipeline bubbles," i.e. holes in the stream of instructions. In a longer pipeline, those bubbles will be larger, once again impacting real-world performance. This is not really true. A deep pipeline will have more bubbles, but each bubble is of shorter duration, so the branch mispredict penalty is not much different in a deep pipeline than it is in a short pipeline. Scumbria