Grove - IA-64 systems to become the power behind the Internet universe.
Yu - Willamette - "a client architecture for a new millennium"
"Willamette is going to give leading performance and frequency for the desktop world."
Timna - will replace the Celeron at the lower end of the market, where "value-priced" PCs selling for less than $600 rule.
eetimes.com
Analysis: Intel shows CPU strategies to dominate Internet computing
By Alexander Wolfe
EE Times
(02/18/00, 5:05 p.m. EST)
PALM SPRINGS, Calif. ? Can Intel Corp. drop its competitors with a one-two punch on the client and server fronts? That was the central technology and business question that hung in the air after this week's Intel Developer Forum (IDF), where the company indicated it is determined to tough out what may be the most complex architectural strategies the industry has ever seen in both its 32-bit and 64-bit microprocessor road maps.
On the 32-bit front, Intel will take deep pipelining to new extremes in its next-generation Willamette processor. Details of the completely overhauled microarchitecture include a better branch-prediction algorithm and new instructions to handle double-precision floating-point calculations. Equally important, Willamette will connect to the outside world via a 3.2-Gbyte/second system interface.
Intel's new Williamette processor takes the company's 32-bit road map to higher levels of complexity with a next-generation microarchitecture and a deeply pipelined design.
Meanwhile, in the 64-bit arena, Intel indicated that it's now-sampling Itanium processor will soon be ready to bring its brand of VLIW-oriented computing into the high-end server world. Intel officials said they are getting the final kinks out of the Itanium fab process so that 0.18-micron parts, at 733 and 800 MHz, can roll off one of the company's manufacturing lines later this year.
Work is also proceeding apace with another new 64-bit microarchitecture in the form of Itanium successor McKinley, which is due in 2001, Intel executives said.
Intel's intention to stake its future on two families that push both 32- and 64-bit MPU design envelopes apparently maps directly to its marketing plans, in what the company sees as a computer world driven largely by electronic commerce. (It's also an apparent bid to stave off two competing architectures: Sun's Ultrasparc and Compaq's Alpha.)
In that regard, in his IDF keynote speech, Intel chairman Andrew Grove framed the question as "How do we grow the infrastructure without dealing with software migration issues?" In Intel's view, such issues mean having to rewrite today's 32-bit applications to run on 64-bit machines.
He answered his own question by saying, "The simplest way is just to add more servers." Translated into business terms, that means Grove intends for IA-64 (i.e., Itanium and McKinley) systems to become the power behind the Internet universe. Several such prototype machines were on display at the show from a variety of OEMs.
On the other side of the equation, Intel microprocessor honcho Albert Yu proclaimed that Intel was building "a client architecture for a new millennium" as he demonstrated first silicon of the upcoming 32-bit Willamette. Yu cranked his demo setup to a clock speed of 1.5 GHz, though initial parts will likely ship closer to the 1-GHz range.
"We just got first silicon a month ago and I feel very comfortable about the way it's been running," Yu said. "We are going to be shipping hundreds of thousands [of processors] by year's end and millions next year." A 0.18-micron Willamette is currently ramping at five fabs; six will be running full tilt by the end of 2000, Yu added.
Walking on eggshells
Such optimism stood in stark contrast to the eggshells Intel officials seemed to be treading on at the previous IDF, last fall. There, the company was under the gun to show first silicon of Itanium (then called Merced), which appeared to be falling behind Intel's self-imposed delivery deadline. Once Intel did show first silicon at that forum, the relief among company executives was palpable. At the latest IDF, those same people had moved from tenuous optimism to a full-blown embrace of the IA-64 architecture.
"Internally, we're checking the last speed paths to make sure we'll have high yields," promised Intel vice president Gadi Singer. "Our focus in the second half of 1999 was pushing the frequency [of Itanium] in a consistent and robust manner. Now we just have to qualify the silicon for launch."
Itanium, the first incarnation of IA-64, relies heavily on very-long-instruction-word design. However, Intel has long shunned the term "VLIW" in favor of Epic ? for explicitly parallel-instruction computing ? which it says better describes the variety of techniques brought into play. The IA-64 instruction set was designed jointly with Hewlett-Packard Co.; however, Intel says it will design and make all IA-64 chips itself.
When Itanium systems do start shipping, Singer said it is unlikely we'll see any single-processor models. OEMs have readied two-, four-, eight- and 16-way multiprocessing systems. One OEM is currently debugging a 64-way Itanium model, he said. (Presumably, that machine uses the OEM's own core logic, since Intel itself is not currently supporting 64-way IA-64 operation.) And Singer said that one customer is on the verge of getting involved in a 512-way Itanium design. He added that it's not a government customer ? a supercomputer center, for example. That's significant, because it points to possible aerospace or automotive interest in IA-64.
Singer added that Itanium successor McKinley is currently in the late stages of design.
As for the company's new 32-bit technology, Intel Fellow Glenn Hinton delved more deeply into Willamette at IDF than was expected. "It's a completely new core microarchitecture design," said Hinton. "Willamette is going to give leading performance and frequency for the desktop world."
The processor has a 20-stage branch-misprediction pipeline, as opposed to 10 stages for the P6, the current 32-bit generation. Willamette's arithmetic logic unit (ALU) is double-pumped, running at twice the chip's clock frequency.
However, it's a difficult task to keep such a deeply pipelined chip humming along without any stalls ? that is, "unwanted" instructions ? turning up. Such instructions rear their heads because long pipelines require predicting which instructions will be needed long before actual execution time ? a situation ripe for havoc.
To mitigate such difficulties, Willamette implements the same general class of deeply speculative techniques that's seeing its first flowering in Itanium. In Willamette, more than 100 instructions can be in the pipeline at any one time, and up to 48 loads and stores can be handled.
Specific to Willamette, though, is an improved branch-prediction algorithm. "We have many fewer mispredictions [than other designs]," said Hinton. That's additionally aided by the presence of a large branch target array, a space where "predictions" are held in waiting.
A final design goal was a significant speed-up of floating-point and multimedia (MMX) instructions. This was accomplished through a series of larger registers that handle double-precision calculations. A new kind of Level 1 instruction cache keeps floating-point instruction close to the execution unit, as needed.
Finally at IDF, Intel also talked turkey about Timna. That chip will be highly integrated and will replace the Celeron at the lower end of the market, where "value-priced" PCs selling for less than $600 rule. Timna will combine a P6 core with a memory controller, Level 2 cache and a low-end graphics controller. An off-chip I/O controller will still be required. |
