Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: kash johal who wrote (94340)	2/20/2000 2:16:00 PM
From: Scumbria	Read Replies (1) \| Respond to of 1574485

Kash, I have seen "zero clock skew" done automatically via autorouters. The idea is to essentially add metal routing in the clock to each sequential element to make the overall skew equal. Sure adds to design complexity but sure as hell can be done. "Zero clock skew" is a nice idea, but variations in process from lot to lot will cause clock skew. A 15 million transistor design with tens of thousands of latches probably can not stand to have huge amounts of extra metal routing to balance the clock tree. 200 ps skew would be considered "zero skew" for an ASIC, but for a 3 GHz CPU would be disastrous. Scumbria