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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (94377)	2/20/2000 5:33:00 PM
From: Elmer	Respond to of 1580215

Re: "I know this has been brought up before, but upon further reflection, it might be reasonable to consider Willamette as a non-X86/X87 processor that can nevertheless emulate one - but only at much reduced performance, like Itanium." Dan I'm not an architect so I'm not doing to make a fool out of myself trying to sound like one but it looks to me like some articles seem to contradict this: eetimes.com "A final design goal was a significant speed-up of floating-point and multimedia (MMX) instructions. This was accomplished through a series of larger registers that handle double-precision calculations. A new kind of Level 1 instruction cache keeps floating-point instruction close to the execution unit, as needed. " Other comments: zdnet.com "The floating-point unit also seems to be much improved, but the programming model for non-SIMD floating-point operations is still stack-based, which continues to be an x86 bottleneck. But floating-point multiplies and adds and loads and stores to and from L1 cache can occur every clock cycle."

To: Dan3 who wrote (94377)	2/20/2000 6:03:00 PM
From: Elmer	Read Replies (1) \| Respond to of 1580215

Re: "I know this has been brought up before, but upon further reflection, it might be reasonable to consider Willamette as a non-X86/X87 processor that can nevertheless emulate one - but only at much reduced performance, like Itanium." Dan here's another interesting article on Willamette's SIMD2 instructions. aceshardware.com "Intel is concentrating on ISSE2: No less than 144 new instructions. If Intel can rally enough support behind ISSE2, the Willamette FPU performance will blow everybody else out of the water, as the ISSE2 FPU performance is vastly superior to the x87 in single precision. A dual ISSE2 unit at 1.4 GHz, the clockspeed at which the fastest Willamette will ship (Q4 2000), would boast a peak of no less than 2 x 4 (SIMD) x 1.4 GHz = 11.2 billion floating-point operations per second (or FLOPS)! The x87 FPU would deliver a measly 1.4 GFLOPS peak. For comparison, if AMD manages to introduce a 1.2 GHz Athlon by the time the Willamette ships, the x87 FPU will peak at 2.4 GFLOPS, while the 3DNow! units will peak at 4.8 GLOPS. All of these numbers are theoretical, of course, but it gives you an idea of how powerful such a SIMD implementation can be. " That says the theoretical FP performance of Willamette is 2.333 X Athlon clock for clock when both forego the x87 FPU and use their SSE instruction set. Higher clock speeds would of course widen the gap. EP