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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: kash johal who wrote (94619)	2/22/2000 3:45:00 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 1572336

Kash, L1 cache is tightly coupled to a core's internal pipeline, so it cannot be shared between two cores. That's why each CPU will still have its own L1 cache. IBM's Power4 behemoth will feature dual-core processors. Each core has its own L1 cache. Both cores on the processor will share an L2 cache and an L3 cache tag array. Then four of those processors (i.e. eight cores and four L2 caches) will be placed on a 5x5" module, with a mesh of ultra-high speed proc-to-proc connections. L3 cache will be external to the module; I think each processor will each have its own L3 cache. This would be a lot easier if I could just draw it on a whiteboard, but of course, that's not possible here. Tenchusatsu