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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Epinephrine who wrote (94649)	2/22/2000 8:20:00 PM
From: Elmer	Read Replies (2) \| Respond to of 1576346

Re: "they could be inaccurate is if Johan is wrong in his assumption that Willamette will still only have a single issue FPU or that it will only have one ISSE2 execution unit." Epi currently CuMine FPU performance is very close to Athlon without compiler enhancements, and much better with. And I think it is a mistake to compare Willamette x87 execution with CuMine performance. Consider the following statements: zdnet.com "The floating-point unit also seems to be much improved, but the programming model for non-SIMD floating-point operations is still stack-based, which continues to be an x86 bottleneck. But floating-point multiplies and adds and loads and stores to and from L1 cache can occur every clock cycle." eetimes.com "A final design goal was a significant speed-up of floating-point and multimedia (MMX) instructions. This was accomplished through a series of larger registers that handle double-precision calculations. A new kind of Level 1 instruction cache keeps floating-point instruction close to the execution unit, as needed. " EP

To: Epinephrine who wrote (94649)	2/22/2000 8:28:00 PM
From: steve harris	Respond to of 1576346

Epinephrine, let me translate FUDD's response for you: Willy FPU sucks. "Epi currently CuMine FPU performance is very close to Athlon without compiler enhancements, and much better with. And I think it is a mistake to compare Willamette x87 execution with CuMine performance. Consider the following statements: zdnet.com "The floating-point unit also seems to be much improved, but the programming model for non-SIMD floating-point operations is still stack-based, which continues to be an x86 bottleneck. But floating-point multiplies and adds and loads and stores to and from L1 cache can occur every clock cycle." eetimes.com "A final design goal was a significant speed-up of floating-point and multimedia (MMX) instructions. This was accomplished through a series of larger registers that handle double-precision calculations. A new kind of Level 1 instruction cache keeps floating-point instruction close to the execution unit, as needed. " EP" Make it so, Mysef