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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (95770)	2/29/2000 1:16:00 AM
From: Scumbria	Read Replies (1) \| Respond to of 1573433

Elmer, So it behaves exactly like a 3GHz clock for logic that only runs off the leading edge, except that the weenies who can't drop their old clock oriented mindset keep misleading everyone by pointing out that it only 1.5Ghz buy their obsolete definition. It is not that simple. A 3GHz pipeline would require a pair of master/slave latches (or a flip-flop) on each stage. The clock skew (including jitter), setup time, propagation delay, and hold time through the storage elements would eat up almost the entire cycle. At ISSC this year, Intel presented a paper describing the barriers in achieving > 2GHz design. The authors discussed prominently the very difficult issue of clock skew. It is certainly possible to create a combinational circuit that resolves in 300 ps, but that does not equate to a 3 GHz circuit. We are still a long ways away from 3 GHz processors! Scumbria

To: Elmer who wrote (95770)	2/29/2000 3:55:00 PM
From: Cirruslvr	Read Replies (1) \| Respond to of 1573433

Elmer - RE: "what you just described is EXACTLY what double pumped means" Thanks for the clear up. Ace's has ANOTHER update about Willy's ALU. Apparently now a different Intel rep is saying it IS 3GHz! aceshardware.com and aceshardware.com Johan says this is Intel's official explanation - "The ALU is running at 3Ghz. The clock for the 3Ghz is generated in reference (strobe) to the 1.5 Ghz base clock. Means, if the base clock would be 1.4Ghz, the ALU would run at 2.8Ghz. Effectively the transistors have to switch at a rate required to achieve 3 Ghz (1/3000.000.000 s). This is also called double pumping which could be described as well: The processor could finish a calculation in the first half of the base clock and pass on the data for further actions in the second half of the clock (again base clock). The conclusion is that the ALU latency is 0.5 clocks (in reference to the base clock). To achieve a 0.5 clock latency in both ALUs, the ALUs have to run at the double of the base clock. In this case, it was 3 Ghz." "Cringe" And you wonder why people are sometimes hostile towards you...