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Technology Stocks : ARM Holdings (Advanced RISC Machines) plc. -- Ignore unavailable to you. Want to Upgrade?

To: Mats Ericsson who wrote (434)	4/10/2000 3:36:00 PM
From: Mats Ericsson	Read Replies (1) \| Respond to of 912

Volatile week-naz-3200-target-picoturbo-patents.. CNBC talks 32o0o0o0o nazdad target 'the level before pubblle'; buy that talk brother? Picoturbo- another Risc startup and very disturbing one, with patent etc noise coming in. Picoturbo advertise itself as cheaper solution with arm syntaz (patent case comming?). isdmag.com Picoturbo Introduces RISC Processor Cores. Milpitas, CA---April 10, 2000---Picoturbo, Inc., a Silicon Valley start-up founded to develop, design and market 32-bit RISC processors, announced that it is introducing its product line. The Picoturbo microprocessors, designed specifically for the Silicon Intellectual Property (IP) market, are the first products from an alternate source that offer the capability of executing the ARM v4T Instruction Set, the company said. The Picoturbo family of processors feature higher performance, integrated power management, and a compact die size, according to the company. According to Hong-Yi Chen, chief technology officer and Founder, "We developed these products in a total 'clean room' environment and they are original works of development. We saw that there was huge market demand for embedded processors and that the market was looking for lower-cost, higher performance alternatives to ARM processors. It was our goal and aim to provide the semiconductor industry with a 'better IP solution', which allows designers and developers to rapidly integrate a microprocessor core with the least amount of effort." The product line is comprised of two 32-bit RISC processor cores, the pT-100 and the pT-110 which are available in a fully synthesizble, Verilog RTL format. The pT-100 executes the ARM 7 TDMI Instruction Set, including the Thumb extensions. The core, in .18u process, is only .9 millimeter square and offers power consumption of .45mW/MHz. Built around a 5-stage pipeline, the pT-100 operates at a worst-case frequency of 100 MHz. Power management is integrated into the fully static core and offers designers the ability to disable the processor when it is not required. The Picoturbo pT-110 also executes the ARM v4T Instruction Set while offering a user-configurable Instruction and Data cache. The Instruction and Data cache can be configured in .5kb increments to a total of 32kb each. The flexibility of this feature enables designers to choose from a number of options, such as cache lock down or data streaming, to reduce access time to both data and instructions, the company said. Power management is integrated and Built-In-Self-Test is included for the cache. The pT-110 has a typical frequency of 250 MHz in a .25u process and is fully capable of 300 MHz when fabricated in an .18u process. Concurrent with the announcement of these products, Picoturbo is also releasing a very aggressive road map. The pT-120 is a follow on product that will incorporate all of the features of the pT-100 and pT-110 and key enhancements to support the emerging market demands. The pT-120 will incorporate a Memory Management Unit (MMU) and Branch Prediction. It will also be capable of executing the ARM Instruction Set and will be binary compatible with the other Picoturbo products. It is expected, when fabricated on .18u process, that the pT-120 will have a frequency of 500 MHz. The pT-120 has taped out and is expected to sample early in the second quarter of 2000. The Picoturbo architecture is available for licensing now. Designed to a process portable .25u or .18u rule-set, both processors can be integrated as an embedded core within an application or product specific design and are offered in a synthesizable format. Pricing is proprietary and available on a quotation basis. For more information contact: Picoturbo, Inc. Milpitas, CA www.picoturbo.com Return to Headlines