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To: Joe NYC who wrote (96186)	3/2/2000 1:36:00 AM
From: Scumbria	Respond to of 1576659

Joe, With these 128 bit instruction words, that contain 3 insturctions, isn't there going to be a problem with cache misses? Suppose you have these 3 instruction, each of these instructions needs some data that is sitting somewhere in memory. The compiler does not know where. Suppose 2 of them are in L1, and the third one is not even in L2 and has to be retrieved from main memory. What's going to happen with this instruction? Isn't it going to be stalled until the data is retrieved? I suspect that the cache will be organized so that the entire 128 bits is contained within a single cache line, so it is not possible to get a partial hit. The poor code density will cause a lower hit rate in the cache, meaning as you said more cache misses. Scumbria

To: Joe NYC who wrote (96186)	3/2/2000 3:05:00 AM
From: Tenchusatsu	Read Replies (1) \| Respond to of 1576659

Joe, <Suppose you have these 3 instruction, each of these instructions needs some data that is sitting somewhere in memory. The compiler does not know where. Suppose 2 of them are in L1, and the third one is not even in L2 and has to be retrieved from main memory. What's going to happen with this instruction? Isn't it going to be stalled until the data is retrieved?> Harsh Sharangpani at MPR last year said that a common misconception of Itanium is that it will be a completely static architecture. Instead, Itanium will allow some out-of-order execution, with a register scoreboard at the end to retire instructions in-order. Harsh called it "the right level of smarts." This allows other non-dependent instructions to execute while one is waiting on a load or doing something else. Tenchusatsu