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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (96265)	3/2/2000 3:51:00 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 1576807

Joe, <Does this mean that the processor will be able to unpack the individual instructions from the group of 3 and execute them, or that it will put this 3 instruction group on hold, and try to execute another one out of order?> I think your first answer is correct. Merced can issue up to two bundles of instructions (w/ a max of three instructions per bundle) to the execution units in one clock. After the bundles are issued, each instruction can be considered "unbundled." Here's what MPR has to say about the back-end part of the Merced pipeline: Merced does not reorder instructions as out-of-order RISC or CISC processors do. But due to the different latencies of integer math, loads, FP math, and cache misses, instructions can finish executing out-of-order. The processor employs a register scoreboard to determine if a target register has been updated. As long as no instruction requires the result of a multicycle operation, the pipeline continues flowing normally. It stalls only if an instruction attempts to access a register that the scoreboard indicates is unavailable. Hope that makes sense to you. Tenchusatsu