Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (98625)	3/16/2000 1:41:00 AM
From: Scumbria	Respond to of 1570684

Dan, If Willamette's 20 stage pipeline is run "double-pumped" so that all instruction must complete within 10ns on a 1GHZ CPU, is it going to be any easier to scale than a Thunderbird or Mustang that single pumps its 10 stage pipeline? The instruction latency (the amount of time which the instruction is in the pipeline) is only important on branch misprediction. What is important is the number of instructions completed per second (measured in MIPS.) A deep pipeline like Willy has requires less work per pipe stage, which means fewer gate delays per pipe stage. The deep pipeline translates directly into higher frequency than the shorter Athlon pipeline. Has Willamette also added more stages for instruction decoding, etc? Does Willamette give itself more time to schedule an instruction? Or is it the same twice as many half the size system? (or just similar clock counts for decoding?) The Willy pipeline has only one execute stage. The entire rest of the pipeline is devoted to the various data retrieval and control functions you described above. Interestingly enough, decode is not part of the normal pipeline, because Willy has a trace cache which contains already decoded instructions. Scumbria