Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Goutam who wrote (98791)	3/17/2000 9:54:00 AM
From: Scumbria	Read Replies (1) \| Respond to of 1571175

Goutama, Besides latency (effects of which can be offset from the gains with the resulting higher clock rates), are there any other reasons (die size,... ?) why it requires the management to be convinced in adopting deep pipelined designs? Also at what level (depth of the pipe line) the gains due to deep pipe line start leveling off? The problem isn't latency, it is the fear of latency. As long as the pipe is kept full, latency is irrelevant. This concept is not intuitive, and evades most architects and other decision makers. Which processors score highest on benchmarks? The ones with the deep pipelines of course! (Alpha, Athlon, PIII) A deep pipe may or may not require more transistors. Deep pipes are simpler, and generally require less control logic. On the other hand, more latches are required to save state. Power consumption tends to scale upwards with performance, whether it is achieved through higher IPC or higher MHz. The optimum pipeline depth is a function of the delay through the latches. If most of the cycle time is taken up in saving state, the pipeline is not efficient. A 20 stage pipe is about as deep as is practical with current latch designs and clock skews. Scumbria