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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (99218)	3/21/2000 1:36:00 AM
From: kapkan4u	Read Replies (2) \| Respond to of 1576615

<By speed, I assume that you are talking about architectural performance. The L2 cache on Thunderbird actually may have the effect of slowing the clock speed down. It is entirely possible that the MHz advantage that Athlon currently has over PIII may be due to the full speed L2 on Coppermine. Anyway, I'm guessing that the Thunderbird cache will be a small victim cache, and will increase architectural performance by about 5-15%. It remains to be seen if the onboard L2 cache was a good idea. In fact, we may never know....> Wow, Scumbria how could you get so many things wrong in the span of two paragraphs? Kap

To: Scumbria who wrote (99218)	3/21/2000 2:20:00 AM
From: Jim McMannis	Respond to of 1576615

RE:"Anyway, I'm guessing that the Thunderbird cache will be a small victim cache, and will increase architectural performance by about 5-15%. "... Like how much L2 cache? What abut the effect of copper getting the Mhz and/or architectural speed up? Jim

To: Scumbria who wrote (99218)	3/21/2000 2:50:00 AM
From: Charles R	Respond to of 1576615

Scumbria, <The L2 cache on Thunderbird actually may have the effect of slowing the clock speed down. > What makes you say this. <It is entirely possible that the MHz advantage that Athlon currently has over PIII may be due to the full speed L2 on Coppermine.> This is even more interesting. The current data points seem to suggest that it is the other way around. Chuck

To: Scumbria who wrote (99218)	3/21/2000 9:24:00 AM
From: vince doran	Read Replies (1) \| Respond to of 1576615

Scumbria, Kap, Jim: Re speed increase from full-speed L2: There are two data points that should be remembered - 1. Katmai -> CuMine > 20% increase per clock. 2. The odd DDR full-speed cache experiment reported late dec. 99, with one benchmark, on the SuperPi calc. On that bench, standard Athlon 1100 MHz = CuMine 900 MHz, but for the DDR beast, Athlon 835 MHz = CuMine 1050 MHz. That was off-chip, with 24 cycle latency, per JC. The list of SuperPi is at www16.big.or.jp Cheers, Vince P.S. Search JCs for dec with athlon ddr cache to see his post; Ace's had more detail at the time but their archive doesn't work for me.