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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Hans de Vries who wrote (99442)	3/23/2000 11:18:00 AM
From: Daniel Schuh	Respond to of 1571611

Hans, I'd like to go back to your original post, Message 13227411, just for some clarification. My reading of it, in conjunction with the slow shift/multiply info from the developer's guide, is that what's meant by feedback in the ALU is for multiple cycle operations. That is, the ALU can shift 1 bit per pass through the ALU, so any multibit shift will take multiple cycles to complete, just within the ALU stage of the pipe. I assume multiplication is the same thing, a multi cycle composition of adds and shifts, and that the rest of the pipe stalls while the ALU grinds away. I don't know what "logic function feedback" would be used for, in terms of multi cycle operations, but from the way you diagrammed the ALU, it looks like the main advantage of the doubled clocking is getting the add/subtract feedback delay for mult/div down to 1.5 cycle instead of 2 cycles. Doing variable length shifts at 1.5 cycle per bit instead of 2 would seem, er, a pretty fluffy reason to go through the trouble. It's been a long time since I studied computer architecture, and my knowledge of logic design is rudimentary at best, so I'm guessing here. Where did you get the info in your original diagram from? Was that from an IDF presentation? It seems really detailed compared to all the other stuff I heard from IDF, any pointers to more info at that level? Cheers, Dan.