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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: brushwud who wrote (99526)	3/22/2000 8:15:00 PM
From: Jim McMannis	Respond to of 1571036

RE:""On the Celerons, however, Intel is disabling half of the cache and likely running it at a slower speed, so the chip can only take advantage of 128KB of the cache." What is the sensible reason for disabling half the cache? Demand is good?" One reason for this could be that Intel wants to give customers "more value". <G>

To: brushwud who wrote (99526)	3/22/2000 8:20:00 PM
From: Scumbria	Read Replies (2) \| Respond to of 1571036

brushwd, What is the sensible reason for disabling half the cache? Demand is good? Market differentiation. Do you remember the 486SX? It was identical to the 486DX, except that the Floating Point Unit was disabled. Compaq once sold an ISA box for $500 less than an identical EISA box, with minor modifications to disable the EISA pins. This triggered the beginning of their huge stock run up in 1993! Scumbria

To: brushwud who wrote (99526)	3/22/2000 8:30:00 PM
From: Elmer	Read Replies (1) \| Respond to of 1571036

Re: "I guess you should know since you do work at an Intel fab" I do not work at an Intel fab however I do visit them occasionally. Re: "But the article said, 'On the Celerons, however, Intel is disabling half of the cache and likely running it at a slower speed, so the chip can only take advantage of 128KB of the cache' What is the sensible reason for disabling half the cache? Demand is good?" Intel needs a product to fit the Market formerly held by the PII version of Celeron. I'm kind of surprised they are using the same die as CuMine because I expected them to use a seperate die and save the realestate but I guess they decided otherwise. If you are wondering why they aren't actually defective CuMines, there are a bunch of reasons but the simplist is that they just don't get nearly enough defective CuMines, let alone L2 specific defects, to meet the demand for Celerons and they have to plan well in advance to (hopefully) meet the demand. There has been talk of K6-2+s being K6-3s with defective L2s. If this is true, and I don't know that it is, then it really brings into question AMD's die cost structure. If they have enough defective parts to actually recover some in this fashion and productize them, then they have a very high defect rate and many more parts must be unrecoverable. I don't know this to be true but I'm just commenting on reports. EP

To: brushwud who wrote (99526)	3/22/2000 11:41:00 PM
From: tejek	Read Replies (1) \| Respond to of 1571036

On the Celerons, however, Intel is disabling half of the cache and likely running it at a slower speed, so the chip can only take advantage of 128KB of the cache." What is the sensible reason for disabling half the cache? Demand is good? brushwad, Demand is too good! Intel figures that if consumers encounter problems with their pc's microprocessor, they may stop buying, causing demand to slack off and allowing Intel to catch up. ted

To: brushwud who wrote (99526)	3/23/2000 3:24:00 AM
From: Charles R	Read Replies (2) \| Respond to of 1571036

<"On the Celerons, however, Intel is disabling half of the cache and likely running it at a slower speed, so the chip can only take advantage of 128KB of the cache." What is the sensible reason for disabling half the cache? Demand is good?> I have commented on this a few times. There are a lot of advantages for Intel to go with a single die strategy for the time being. See: Message 12875594 That should also explain why you will see higher speed Celerons shortly and also explains why K6-2 didn't have a chance on the desktop side. Intel could have taken a whole bunch of momentum from AMD at the low-end had the 600MHz Celeron showed up in February as rumored but it did not. Now, Spitfire is imminent and could be positioned against PIII in speed grades and performance. In the interim AMD can downbin current Athlons or sell a few "limited edition" K6-2s to compete in the 600MHz space and still make good money. Assuming AMD can successfully pull off this transition in Q2, Q2-Q4 will be phenomenal quarters.