To: tejek who wrote (99660 ) 3/23/2000 9:54:00 PM From: Dan3 Read Replies (1) | Respond to of 1574493
Re: I thought DRAM allowed much more bandwidth and speed... SDRAM = synchronous dynamic random access memory RDRAM = rambus dynamic random access memory DDRDRAM = double data rate dynamic random access memory All are dynamic random access memory DRAM, as opposed to SRAM = static random access memory DRAM stores information in capacitors that steadily lose charge and must be periodically refreshed (hence the "dynamic") If a cell is being refreshed when the system tries to access it, the system must wait for the refresh to complete. SRAM is always ready, but uses more power and takes up more chip space. Cache RAM is always SRAM. SDRAM is 64 bits (8 bytes) wide and runs at 100, 133, and (rarely) higher. Data rate is 8 bytes x 100MHZ = 800meg/sec or 8 x 133 = 1064 MB/sec. DDR DRAM is 64 bits (8 bytes) wide and runs at 200, 266, 333, 366, and 400 MHZ data rate (1/2 that speed, double data rate) x 8 or 1,600, 2,128, 2,664, 2,928, and 3,200 MB/sec. DDR DRAM is 16 bits (2 bytes) wide and runs at 566, 712, and 800 MHZ data rate (1/2 that speed, double data rate) x2 or 1,132, 1,424, and 1,600 MB/sec. 2 1,600 MB/sec rambus channels can be combined to equal one 3,200 MB/sec DDR channel. Rambus uses wide data paths on the silicon of the memory chips to allow for 8 cells to be comined into one. The internal data paths on a rambus chip are 128 bits wide. These paths take up more of the chip than other types of DRAM. Rambus chips also have to have logic circuits that collect the data and put it into packets. The logic circuits must run very fast, the rest of the chips doesn't. This size, speed, and complexity increase is why Rambus costs so much more than other types of DRAM. Rambus memory channels are narrower (but faster), so it's easier (and necessary) to put multiple channels on a board. Intel's 840 motherboard uses 2 rambus channels to make up for rambus's 16 bit data bus. Rambus is a high speed serial protocol that adds a brief delay to memory transfers while the chip collects data from 8 cells and combines them into a packet which is then sent along the bus - SDRAM and DDR DRAM connect the chipset directly to the memory cells using a simpler (but slower) protocol. Regards, Dan