RTEC.....Changes in materials and process steps for dual-damascene copper
interconnects are also expanding the need for multi-layer metal-film metrology,
says George J. Collins, director of marketing at Rudolph Technologies Inc. in
Flanders, N.J. The trend towards cluster tools is driving the need for "pretty
sophisticated metrology for bi-layer stacks," he says.
Rudolph is promoting its non-contact MetaPULSE, which uses a picosecond
ultrasonic laser sonar technique called Pulse Technology, to measure multiple
layers of opaque films that can't be done with optical metrology. Ultrasonic
metal-film metrology is now gaining favor in post-CMP measurements to detect
"dishing" and unwanted erosion from polishers at small spots on the wafer
surfaces, he says.
..............Fab Strategies: Move to copper gets serious
With 300-mm wafer on back burner, copper called "next market
mover;" More than a dozen chip makers will be running volume lines
within a year
By J. Robert LIneback
Semiconductor Business News
(03/28/00, 02:00:49 PM EDT)
The chip industry's big transition from aluminum to copper interconnects is finally
underway -- bigtime.
After a couple of years of uncertainty, marketing hype, and yield scares, the move
to copper is accelerating at most major chip makers.
Expectations were running high on copper a year ago, but the progress made was
less than most forecasts had called for "because of bad publicity about low yields
and concerns about copper contamination," says analyst Robert N. Castellano,
president of The Information Network. An uncertain chip market outlook didn't help
either.
This is definitely copper's year, says the
New Tripoli, Pa., market researcher.
"With 300-mm [wafer fabs] still on the
back burner, our analysis shows copper
technology is the next market mover,"
Castellano says.
The rising growth in sales of copper
processing tools backs this optimistic
outlook. Revenues from copper tools
climbed 36% last year to $745 million,
and a new forecast from The Information Network is calling for a 50% increase this
year, pushing global sales of copper gear to $1.13 billion.
Already, IBM, Motorola, and Advanced Micro Devices are ramping up production
of copper-based ICs. And nearly a dozen other producers will join them in
launching volume processes over the next 12 months. The competition is really
hot in Asia, where the world's three largest silicon foundries are racing to offer
copper technology to their broad customer bases of fabless chip companies.
Giving copper a big boost now is the dramatic improvement in business
conditions. "The biggest change [from a year ago] is that the business cycle fully
recovered," points out Ken Monnig, associate director of the Interconnect Group at
International Sematech in Austin, Tex.
And chip makers have been able to gain experience with the new process. "The
processes are a little more mature, particularly copper plating," Monnig says. "We
have more learning on consumables, such as slurries and polishing pads." And
chip makers moving to copper "have a better portfolio of reliability information."
"We're not yet to the point where copper processes can be run with our eyes
closed, but the industry has made a lot of progress fine tuning tools and the
technology," acknowledges the semiconductor R&D consortium executive.
"There's still work to do and problems to be solved, such as polishing in [chemical
mechanical planarization], and post-polishing steps."
Ready or not?
One problem that slowed things down last year was that fab equipment suppliers
were not able to fully deliver production-ready processes along with their copper
tools, Monnig notes.
"For some semiconductor manufacturers, this was the first time they tried to buy
'turnkey processes,'" he says, "and these bundled technologies did not work as
expected." The Sematech executive notes that none of the equipment suppliers
"could supply fully debugged process flows." That caused "some of the initial
confusion about yields disasters in the press," he adds. (See related story on
copper process selection.)
But major tool suppliers for dual-damascene copper processes are optimistic
about the progress that will be made this year in the migration from aluminum
interconnects. "This year you will see a lot of companies switching from
development to mass production as they follow in the footsteps of IBM," predicts
Wilbert van den Hoek, executive vice president of integration and development at
Novellus Systems Inc. in San Jose.
While executives at rival Applied Materials Inc. agree with this outlook, they also
point out that most chip makers still need hand-holding and additional support to
overcome initial concerns about yields. As a result, Applied plans this year to roll
out a series of customizable copper technology modules for integrated tool sets
and guaranteed process results.
"Copper is ready now to move from R&D to high-volume manufacturing at certain
customers, but not across the board yet," explains Ashok K. Shinha, president of
Applied's Interconnect Systems and Modules Business Group in Santa Clara,
Calif.
Copper processing will probably get its
biggest boost this year from the world's
largest pure-play silicon foundries. These
dedicated foundry companies are pushing
hard to narrow the gap between their
production lines and those of the big chip
companies called IDMs (integrated device
manufacturers) which are running their
own fabs.
Taiwan Semiconductor Manufacturing Co.
Ltd. (TSMC) and rival United Microelectronics Corp. (UMC) both have begun
fabricating copper IC prototypes last year and are offering processes for
production ramps with 0.18-micron technologies this year. Also coming from the
two Taiwanese foundries this year are next-generation 0.15-micron copper
processes.
And in Singapore, Chartered Semiconductor Manufacturing Pte. Ltd. also is about
to start producing prototypes of copper ICs with two different dual-damascene
processes--one transferred from Motorola Inc. under a foundry alliance and the
other jointly developed with partner Lucent Technologies Inc.
But this is a hard move for producers to make. "Aluminum interconnect has
served us well for three, maybe four decades, and there is significant inertia to
overcome because of the large knowledge base built around aluminum," notes
John Martin, Chartered's vice president of technology development. "We will see
aluminum-based products serving certain customer requirements certainly through
the 0.15- micron and maybe the 0.13-micron node," he predicts. "But at
0.18-micron technology, the gradual transition [to copper] will begin with
microprocessors and shift to very broad applications at 0.13 micron and below
feature sizes."
"Risky" business
This migration to copper presents a unique problem for the dedicated foundries.
As contract wafer fabricators, they must quickly find customers willing to act as
learning-curve partners in what TSMC calls "risk production."
"It is a Catch-22 situation," declares Sheld Wu, a member of TSMC's North
American technical staff in San Jose. "TSMC must demonstrate the ease of use
and the reliability of copper. That is why we must make copper accessible as
early as possible to our customer base so we can move on the learning curve
together."
TSMC has ambitious plans. By the end of 2000, it expects to have fab capacity
for 40,000 copper layers per month available to its foundry customers. "If we are
talking six-layer, all copper metalization, that would be enough to do more than
6,000 wafers per month," Wu points out.
In mid-March, TSMC announced that copper technology will be available with its
new 0.15-micron technology. By the end of the year, this process will be running
in two 8-inch fabs in Hsinchu, Taiwan. When TSMC makes its 0.13-micron
processes available to customers early next year, it expects to offer only copper
interconnects in that technology generation.
UMC in late March announced it was shipping 0.18-micron copper-process wafers
to its technology partner Xilinx Inc. of San Jose, which now claims to be the first
supplier of field-programmable gate arrays with copper interconnects. UMC is also
in a process alliance with IBM and Infineon Technologies AG for 0.13-micron
all-copper processes (see Jan. 28 story). TSMC is teamed with programmable
logic supplier Altera Corp., which expects to receive early prototypes of all-copper
0.13-micron chips this year from its foundry partner.
The silicon foundries are aiming to make advanced copper technology "available to
the third-tier semiconductor companies that do not rely on their own processes,"
notes Novellus' van den Hoek. "That is putting the major IDMs under more
pressure to make copper available in their own fabs for their own products," he
points out. "Some IDMs will suddenly find themselves behind, if they aren't
careful."
This fear of falling behind in interconnect technology is now replacing chip makers'
concern over learning how to work with copper and its lower yields. In fact, some
of them now are taking the easy route to copper by using it on only the top two
layers of interconnect.
Some managers warn that this mixing of copper and aluminum will delay the
additional learning steps that are needed to put full-copper, dual-damascene
processes into volume production when technology requirements make aluminum
wiring no longer feasible. This will probably happen around the 0.13- or 0.10-
micron technology node, experts predict.
Once IC makers succeed in building a chip using copper only in the top two or
three interconnect layers, they often see production yields drop significantly when
they switch to all-copper designs, warns Novellus' van den Hoek. "A lot of the
process integration issues do not show up when you only put down two layers of
copper," he declares. "People have started to see that happen."
Look, no aluminum!
Copper pioneers IBM Corp. and Motorola Inc. are using the metal on all levels of
interconnect--four to seven layers--in new IC designs with 0.18-micron feature
sizes. The two companies began copper processing on all layers of interconnect
partly to accelerate yield learning curves. As a result, both companies now believe
that all-copper devices are much easier to produce than hybrid interconnect
structures with aluminum wiring on the lower layers.
"Our copper processors have six levels, which provide more learning," says Bill
Dunnigan, vice president of die manufacturing at Motorola's Semiconductor
Products Sector in Austin, Tex. "Ultimately, everyone will have to get there. The
question is," he asks: "how much risk are you willing to take?"
Motorola has also found that all-copper interconnect technology is simpler to
manage in volume wafer fabs. "You don't have to worry about keeping copper and
aluminum separate and there is more flexibility since you are not having to
manage bottlenecks for some layers of aluminum and some layers of copper,"
Dunnigan points out.
This year, Motorola plans to expand its use of copper from the current lineup of
high-performance SRAMs and RISC microprocessors to digital signal processors
(DSPs), network processors, and ICs for wireless systems applications.
IBM Microelectronics is also moving fast in ramping its copper IC production. The
company said earlier this year that it already had fabricated more than 2 million
copper processors and was now fanning out the metal technology to a wider range
of chip products as well as offering it to silicon foundry customers.
The transition to copper manufacturing began a year-and-a-half ago at IBM, and
now has reached the point where all new technology generations will be designed
with all-copper interconnects, says Russ Lange, a fellow in IBM Microelectronics
Research in Fishkill, N.Y. Only new IC designs with higher voltage requirements
(3.3-V and above, for example) will be candidates for aluminum interconnects in
the future, he adds.
IBM targets low-k
Next on IBM's ambitious copper technology roadmap is switching to low-k
dielectric films, replacing the silicon-dioxide insulators now employed in the
company's dual-damascene processes. "We have an impressive low-k roadmap,
but I cannot talk about it now," says Lange. He did hint that the next-generation
dielectric will not be fluorinated silicon glass (FSG) or any other doped versions of
silicon-dioxide, which are being used by other chip makers to lower dielectric
constants slightly from the 4.1 level of SiO2.
IBM plans to introduce a series of low-k
materials to serve as next-generation
insulators and get around the capacitance
problems in interconnects. The first one
will be disclosed later this year. "We
believe we will be in the leadership [of
low-k dielectrics], just like copper," says
a confident Lange. "We didn't show the
industry what we were doing in copper
until we were ready to start aggressively
using it," he notes, referring to IBM's
surprise technology announcement in
1997 which sparked the industry's copper rush (see coverage from SBN's
magazine, October 1997).
Like IBM, most major chip makers are introducing copper processes first before
they decide on the low-k dielectrics to use in place of silicon dioxide. IBM opted
to focus on copper first because it was the only viable metal to replace aluminum
in ICs. The low-k dielectric candidates have become a confusing array of options.
Before deciding on a low-k dielectric, IBM wanted to completely change the
sequence of interconnect process steps for a dual-damascene flow. It wanted to
etch the dielectric insulator, follow up with the copper barrier and seed deposition,
electroplate the copper fill, and then do the planarization of that layer with CMP
polishers. It has taken chip makers many years of R&D to move from the
conventional subtractive metal etch sequences used in mainstream aluminum
processes.
To extend the life of aluminum as an interconnect, many fabs have increased the
thickness of interconnect lines on the top layers of metal. But that has made it
more difficult to deposit new low-k dielectrics, points out IBM's Lange. "It's like
trying to fill the insulators down to the street level in Manhattan between all the
high-rise buildings," he adds.
The aluminum diehard
Not every producer has given up on doing low-k dielectrics first with existing
aluminum process steps, however. Perhaps the biggest aluminum-interconnect
diehard is LSI Logic Corp., which believes low-k dielectrics must be established
first before tackling the transition to copper metal.
"The ultimate solution--probably [implemented] around the 0.10-micron
generation--will be a mixture of low-k and copper," believes Ronnie Vasishta,
senior director of technical product marketing at the Milpitas, Calif.-based chip
maker. "It will be easier to implement copper into a stable low-k process, if you
want to engineer the ultimate solution."
LSI Logic claims it moved ahead in low-k dielectric processes after it partnered in
process and materials development with Trikon Technologies Ltd. of Newport,
Wales. The chip maker has incorporated Trikon's Flowfill deposition steps and
thin-film material in its 0.18-micron G12 technology. A 0.13-micron process,
called Gflx, was disclosed by the Milpitas, Calif., chip maker in March using the
Trikon Flowfill material. This film results in a dielectric constant of 3.1 once the
interconnects are placed on integrated circuits, according to Vasishta. Fluorinated
silicon glass (FSG)--a popular choice for the initial step to lower dielectric
constants--has a rating of 3.6 to 3.7 once interconnects are processed, he notes.
To make its final move into copper, LSI Logic partnered with Japan's Hitachi Ltd.
The Silicon Valley company still doesn't like the yields that are being obtained
from current copper processes. "They are not where they need to be for volume
manufacturing," Vasishta argues.
If LSI Logic had wanted to introduce copper in its 0.18-micron technology, it would
have ended up delaying the launch because of bad yields. "I would say the copper
yields today are still 50% lower than standard aluminum," Vasishta figures.
Despite all the attention that has been give to copper in the past couple of years,
"it is still far off the radar screen compared to the volumes of chips made with
aluminum," declares Peter Nunan, vice president of strategic alliances at San
Jose's KLA-Tencor Corp., world's largest metrology supplier. Assuming that IBM's
annual output will soon approach 4 million copper chips, such a run rate would
represent no more than six weeks of production in a typical megafab, he
estimates.
Avoiding voids
"We have 30 years of aluminum experience, [but] now we must understand a
completely new set of defect mechanisms," Nunan says. "The top three issues
are voiding, voiding, and voiding," he quips, referring to killer defects resulting from
pockets of missing metal in interconnects.
"Voiding just doesn't manifest itself [at a single process point]. The voids could be
caused by the [copper] plater, etch processes, or PVD [physical vapor deposition
used in copper barriers and seeds]," he says. "How well is post-CMP understood
and could it be the origin of defects? he asks. "How did defects evolve through the
entire process? This is the learning that is going on now in copper processing."
Nevertheless, Nunan is still optimistic, even though he cautions that it will take
volume production of 40,000 copper wafers a month to get a handle on potential
yield-lowering defects. He expects that most of the learning curve will be achieved
in the next couple years, but KLA-Tencor is now trying to convince process
developers to do something they haven't had to do in the past: build in inspection
and metrology as part of the process flow.
"Until now, people have added metrology as an afterthought," says the
KLA-Tencor vice president.
Changes in materials and process steps for dual-damascene copper
interconnects are also expanding the need for multi-layer metal-film metrology,
says George J. Collins, director of marketing at Rudolph Technologies Inc. in
Flanders, N.J. The trend towards cluster tools is driving the need for "pretty
sophisticated metrology for bi-layer stacks," he says.
Rudolph is promoting its non-contact MetaPULSE, which uses a picosecond
ultrasonic laser sonar technique called Pulse Technology, to measure multiple
layers of opaque films that can't be done with optical metrology. Ultrasonic
metal-film metrology is now gaining favor in post-CMP measurements to detect
"dishing" and unwanted erosion from polishers at small spots on the wafer
surfaces, he says.
Comfy with copper
Wafer fab managers are becoming more comfortable with the notion of copper
materials in silicon-processing frontends, according to Adrian Kiermanz, senior
director of product marketing for copper at Lam Research Corp. "Copper
contamination is less of an issue," he adds. "Although people are certainly aware
of it, it is no longer a panic situation."
Something that remains a major challenge, however, is the integration of process
steps and materials, especially when fabs attempt to introduce new low-k
dielectrics with copper dual-damascene technology. "It is still pretty much wide
open," Kiermanz says. "Across the industry, companies still have not completely
settled on which dual-damascene scheme to use. Some etch the [interconnect]
via first and then the trench [for metal lines], while others etch the trench first."
One other concern that's not fully being addressed now at most fabs is backside
wafer contamination, warns Michael West, director of new business development
for Austria's SEZ Holding AG, which supplies spin-processing tools for wafer
surface conditioning. "Cross [tool] contamination is an issue," he says. "What's
on the backside--a nitride or oxide [protective film] or bare silicon?" he asks.
"Unless this is figured out by the big equipment suppliers and IC makers, it will
throw a big monkey wrench into the movement," he warns.
At issue is whether a process step is a batch or single-wafer tool. "My concern is
that some companies are doing single-wafer processing, but they are leaving the
wafer bare with no coating on the backside," West says. With integrated
platforms, wafer cleaning and annealing could be problems because cleaning
[copper from the back sides of wafers] is not sufficient," maintains the Tempe,
Ariz.-based SEZ manager.
In general, though, companies are moving down the learning curve in many of the
copper process steps as aluminum gets closer to the end of the line--something
that probably will hit leading-edge technologies before the middle of the decade.
But in the past couple of years expectations have been inflated by too much
spotlight and attention on copper processing after IBM's big announcement in
1997. "I don't think copper was so much over-hyped as it was misunderstood,"
notes Dana Scranton, director of strategic marketing at Semitool Corp. in
Kalispell, Mont., an early leader in supplying electrochemical deposition tools to
do copper electroplating for metal lines and vias. "We are now at the very early
stages of implementing commercial devices and now seeing production orders."
Many early copper users are now turning their attention to optimizing the metal in
interconnect architectures in order to get the most out of low resistance and
immunity from electrometal migration-something that can cause failures in thin
wiring lines on ICs.
"Originally, people were evaluating low-k [processes first], but over the last two to
two-and-a-half years they have concluded that copper is easier to implement,"
says Tom Ritzdorf, director of technology for electrochemical deposition at
Semitool. "Optimization of copper will give you lower capacitance even if you do
not use low-k dielectrics by making metal lines smaller and a little more room
between them. We'll see that [optimization of copper in designs] happening as
companies mature their processes."
The move to copper has hit nearly all wafer fab tool suppliers in one way or
another. Wafer furnaces, for example, are being installed in copper processing
pilot lines for annealing steps. "People have played with it [the process steps],
worked out the big bugs in manufacturing, and now they are starting to move it
into manufacturing," notes Aubrey Helms, vice president of technology at Silicon
Valley Group Inc.'s thermal systems division.
Smooth sailing for now?
"I don't think there are any technical surprises left," says the San Jose-based
Helms. "Maybe in two device generations [around the 0.10-micron node] there will
be new issues concerning the thickness of barriers [preventing copper from
seeping into the silicon and other materials], but now companies are moving
forward," he predicts.
Currently, about 10 major chip makers are running dual-damascene copper
processes in pilot fabs or full production, estimates Novellus' van den Hoek. In the
U.S., IBM, Motorola, and AMD are well into production, with T |
