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To: Bilow who wrote (39075)	3/30/2000 5:57:00 AM
From: Bilow	Read Replies (2) \| Respond to of 93625

Note on the (recent) history of synchronous memory. From Samsung's .pdf file on the company history: 1993 - "First to offer fully-synchronous Dynamic RAMs" 1992 - "First to offer fully-synchronous SRAMs" usa.samsungsemi.com In fact, SRAMs were the first memory to be made synchronous. Samsung's claim to be the first with fully synchonous SRAMs may be true, but only because they are using the adjective "fully". In fact, synchronous static RAM dates to well before 1992, and pointed the obvious way towards synchronous dynamic rams. Motorola's data book Memory Data DL113 Rev 5, eries F, copyright 1989, previous edition copyright 1988 lists synchronous static RAM, as being in full production (i.e. past sampling, etc.) The parts must date to well before 1988, though I don't have any older memory data books. Anyway, a typical part was the MCM6292, on page 5-25. When the above parts came out, it was clear that the same thing could be done with DRAM, and everybody started asking design engineers what we would do with them. SDRAM wasn't invented in a JEDEC meeting, it was, in my opinion, an obvious extension of the prior art. In fact, I really doubt that the above SRAM is the first synchronous RAM, that data book is one of the few which seems to have escaped by periodic cleansing of my data library. I am sure that ancient super computers used synchronous RAM in main memory. I should explain why the MCM6292 isn't classified as "fully" synchronous. The reason is that the part has an output latch instead of an output register. The inputs are registered, though. The reason they put an output latch on it was so that the users could scam a few extra nanoseconds out of the part. As technology advanced, the clocks speeded up to the point where it was pointless to use latches, as they slightly complicated the design. In fact the part had a pipeline of "1.5" clocks. In other words, you could use it in a synchronous system with the inputs registered on the rising edge and the outputs changing on the falling edge. These half synchronous RAMs gave a designer who cared about latency the opportunity to scam a few nanoseconds on the memory, and those were precious nanoseconds. The timing sheets for the part clearly show what would have been in effect fully synchronous operation, given a slow enough clock period, but they could also be used as a latch stage in a level sensitive timing design (which was not uncommon, way back when, in high end designs). -- Carl