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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: milo_morai who wrote (101276)	3/31/2000 10:28:00 AM
From: Scumbria	Respond to of 1570981

Milo, According to one system integrator close to Intel's plans, the reason for this is because the 1GHz Pentium III uses a different stepping to other Coppermines. As of two weeks ago, he said, that particular stepping was not rated for dual usage. In other words, the part does not run properly at 1GHz. Scumbria

To: milo_morai who wrote (101276)	3/31/2000 10:29:00 AM
From: milo_morai	Respond to of 1570981

ERRATA FOR PENTIUM © III PROCESSOR SPECIFICATION UPDATE 11 SUMMARY OF CHANGES The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Pentium III processors. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations: CODES USED IN SUMMARY TABLE X: Erratum, Documentation Change, Specification Clarification, or Specification Change applies to the given processor stepping. (No mark) or (blank box): This item is fixed in or does not apply to the given stepping. Fix: This erratum is intended to be fixed in a future stepping of the component. Fixed: This erratum has been previously fixed. NoFix: There are no plans to fix this erratum. Doc: Intel intends to update the appropriate documentation in a future revision. PKG: This column refers to errata on the Pentium III processor substrate. AP: APIC related erratum. Shaded: This item is either new or modified from the previous version of the document. Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel? s microprocessor Specification Updates: A = Intel © Pentium © II processor B = Intel © Mobile Pentium © II processor C = Intel © Celeron? processor D = Intel © Pentium © II Xeon? processor E = Intel © Pentium © III processor G = Intel © Pentium © III Xeon? processor H = Intel © Mobile Celeron? processor at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, and 266MHz K = Intel © Mobile Pentium © III processor M = Intel © Mobile Celeron? processor at 500 MHz, 450 MHz, and 400A MHz The Specification Updates for the Pentium © processor, Pentium © Pro processor, and other Intel products do not use this convention. ----------------------------------------------- PENTIUM © III PROCESSOR SPECIFICATION UPDATE 12 Summary of Errata NO. kB0 kC0 cA2 cB0 PKG Plans ERRATA E1 X X X X NoFix FP data operand pointer may be incorrectly calculated after FP access which wraps 64-Kbyte boundary in 16-bit code E2 X X X X NoFix Differences exist in debug exception reporting E3 X X X X NoFix FLUSH# servicing delayed while waiting for STARTUP_IPI in 2-way MP systems E4 X X X X NoFix Code fetch matching disabled debug register may cause debug exception E5 X X X X NoFix Double ECC error on read may result in BINIT# E6 X X X X NoFix FP inexact-result exception flag may not be set E7 X X X X NoFix BTM for SMI will contain incorrect FROM EIP E8 X X X X NoFix I/O restart in SMM may fail after simultaneous MCE E9 X X X X NoFix Branch traps do not function if BTMs are also enabled E10 X X Fixed Checker BIST failure in FRC mode not signaled E11 X X Fixed BINIT# assertion causes FRCERR assertion in FRC mode E12 X X X X NoFix Machine check exception handler may not always execute successfully E13 X X X X NoFix MCE due to L2 parity error gives L1 MCACOD.LL E14 X X X X NoFix LBER may be corrupted after some events E15 X X X X NoFix BTMs may be corrupted during simultaneous L1 cache line replacement E16 X X X X NoFix EFLAGS discrepancy on a page fault after a multiprocessor TLB shootdown E17 X X X X NoFix Near CALL to ESP creates unexpected EIP address E18 X X X X NoFix Memory type undefined for nonmemory operations E19 X X Fixed Infinite snoop stall during L2 initialization of MP systems E20 X X X X NoFix FP data operand pointer may not be zero PENTIUM © III PROCESSOR SPECIFICATION UPDATE 13 Summary of Errata NO. kB0 kC0 cA2 cB0 PKG Plans ERRATA after power on or Reset E21 X X X X NoFix MOVD following zeroing instruction can cause incorrect result E22 X X X X NoFix Premature execution of a load operation prior to exception handler invocation E23 X X X X NoFix Read portion of RMW instruction may execute twice E24 X X X X NoFix MC2_STATUS MSR has model-specific error code and machine check architecture error code reversed E25 X X X X NoFix Mixed cacheability of lock variables is problematic in MP systems E26 X X X X NoFix MOV with debug register causes debug exception E27 X X X X NoFix Upper four PAT entries not usable with Mode B or Mode C paging E28 X X X X NoFix Data breakpoint exception in a displacement relative near call may corrupt EIP E29 X X X X NoFix RDMSR and WRMSR to invalid MSR may not cause GP fault E30 X X X X NoFix SYSENTER/SYSEXIT instructions can implicitly load null segment selector to SS and CS registers E31 X X X X NoFix PRELOAD followed by EXTEST does not load boundary scan data E32 X X Fixed Far jump to new TSS with D-bit cleared may cause system hang E33 X X X X NoFix INT 1 instruction handler execution could generate a debug exception E34 X Fixed COMISS/UCOMISS may not update EFLAGS under certain conditions E35 X Fixed Transmission error on cache read E36 X X X X NoFix Potential loss of data coherency during MP data ownership transfer E37 X X X X NoFix Misaligned Locked access to APIC space results in hang E38 X X Fixed Floating-point exception signal may be deferred E39 X X X X NoFix Memory ordering based synchronization may cause a livelock condition in mp PENTIUM © III PROCESSOR SPECIFICATION UPDATE 14 Summary of Errata NO. kB0 kC0 cA2 cB0 PKG Plans ERRATA systems E40 X Fixed System bus address parity generator may report false AERR# E41 X X X X NoFix System bus ECC not functional with 2:1 ratio E42 X X X X NoFix Processor may assert DRDY# on a write with no data E43 X X X X NoFix GP# fault on WRMSR to ROB_CR_BKUPTMPDR6 E44 X X X X NoFix Machine check exception may occur due to improper line eviction in the IFU E45 X X X Fixed Performance counters include Streaming SIMD Extensions L1 prefetch E46 X X X X NoFix Snoop request may cause DBSY# hang E47 X X X X NoFix Lower bits of SMRAM SMBASE register cannot be written with an ITP E48 X X X Fixed Task Switch May Cause Wrong PTE and PDE Access Bit to be Set E49 X X X X NoFix Unsynchronized Cross-Modifying code operations can cause unexpected instruction execution results E50 X Fixed Processor will erroneously report a BIST failure E51 X Fixed Noise sensitivity issue on processor SMI# pin E52 X Fixed Limitation on cache line ECC detection and correction E53 X Fixed L2_LD and L2_M_LINES_OUTM performance-monitoring counters do not work E54 X Fixed IFU/DCU deadlock may cause system hang E55 X Fixed L2_DBUS_BUSY performance monitoring counter will not count writes E56 X X Fixed Incorrect sign may occur on X87 result due to indefinite QNaN result from streaming SIMD extensions multiply E57 X X X X NoFix Deadlock may occur due to illegal-instruction/ page-miss combination E58 X X X X NoFix MASKMOVQ instruction interaction with string operation may cause deadlock PENTIUM © III PROCESSOR SPECIFICATION UPDATE 15 Summary of Errata NO. kB0 kC0 cA2 cB0 PKG Plans ERRATA E59 X X X X NoFix MOVD or CVTSI2SS following zeroing instruction can cause incorrect result E60 X X X X NoFix FLUSH# assertion following STPCLK# may prevent CPU clocks from stopping E61 X Fixed Intermittent failure to assert ADS# during processor power-on E62 X X X X NoFix Floating-point exception condition may be deferred E1AP X X X X NoFix APIC access to cacheable memory causes SHUTDOWN E2AP X X X X NoFix 2-way MP systems may hang due to catastrophic errors during BSP determination E3AP X X X X NoFix Write to mask LVT (programmed as EXTINT) will not deassert outstanding interrupt Summary of Documentation Changes NO. kB0 kC0 cA2 cB0 PKG Plans DOCUMENTATION CHANGES E1 X X X X Doc STPCLK# pin definition E2 X X X X Doc Invalidating caches and TLBs E3 X X X X Doc Handling of self-modifying and cross-modifying code E4 X X X X Doc Machine check architecture initialization of MCi_STATUS registers E5 X X X X Doc LOCK# signal prefix operands E6 X X X X Doc SMRAM state save map contains documentation errors There's a large amount of pages that goes into further details apps.intel.com Note allot of this are denoted to never be fixed. Milo

To: milo_morai who wrote (101276)	3/31/2000 10:37:00 AM
From: Epinephrine	Respond to of 1570981

Milo Morai (Milo), From the article you posted: Intel Corporation fully supports mixed steppings of Pentium III processors. Translation: We support not only any stepping but even the use of mixed steppings in SMP configurations. 12. These processors cannot be used in Dual Processor (DP) applications. (referring to 1GHz coppermines) Translation: Except for with our 1GHz freak chip!!! ROTFLMAO!! :) Regards, Epinephrine