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To: Scumbria who wrote (40224)	4/18/2000 1:17:00 PM
From: Tenchusatsu	Respond to of 93625

Scumbria, I was talking about transaction bursts, which is why the P6 and the P6 bus is able to support multiple outstanding transactions. And with Coppermine's increased buffering (a.k.a. Advanced System Buffering), it has the potential to issue more outstanding transactions than previous P6 cores. By your math, a P6 only has to issue one transaction per 100 clocks. That might be true if you average everything over a very large period of time. But the transaction pattern certainly isn't spread out that nicely. Instead, it's more like: Wait 1000 clocks, then issue 10 transactions all at once, then wait another 1000 clocks. By the way, I'm not even sure I agree with the overall average of one transaction per 100 clock. Processor clocks are so much faster than FSB clocks these days, so I'd guess that the overall average is lower, depending on the application. Tenchusatsu