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To: Tenchusatsu who wrote (40450)	4/20/2000 2:02:00 AM
From: Scumbria	Respond to of 93625

Ten, 1) The crossover point of latency between Via/PC133 and 820/RDRAM is 375 MB/sec. With Via/VC133, the crossover point is 450 MB/sec. I can't imagine those figures to be a level of saturation for a 133 MHz FSB. Complete saturation occurs at 512 MB/S, but at 450 MB/S congestion in the VC133 becomes rather severe. DRDRAM is nowhere near saturated at that point. I'm not sure why 840 has lower latency than 820. I have seen comments that it has something to do with interleaving between the 2 DRDRAM ports, though it is not obvious what that accomplishes. Maybe it is due to twice as many open banks, and lower page miss frequency. Scumbria

To: Tenchusatsu who wrote (40450)	4/20/2000 3:13:00 AM
From: The Prophet	Respond to of 93625

Ten: Watcha think about some RDRAM in that there PocketPC device?

To: Tenchusatsu who wrote (40450)	4/20/2000 3:24:00 AM
From: John Walliker	Respond to of 93625

Tenchusatsu, The 840 chipset w/ PC800 RDRAM has an average latency that's 50 nsec better than that of 820. That's almost seven FSB clocks. And this advantage is constant throughout the entire bandwidth spectrum. Certainly this can't be achieved by simply adding just another RDRAM channel. That tells me that something is abnormally crippling the performance of 820. This puzzles me too. I have the figure printed out in front of me right now. The re-entrant behaviour of the Apollo is interesting too. John

To: Tenchusatsu who wrote (40450)	4/20/2000 6:06:00 AM
From: Bilow	Read Replies (3) \| Respond to of 93625

Hi Tenchusatsu; I'll take a swing at some of the latency difference between i820 and i840 in that chart. (I should mention that I don't know how the chart was generated, and therefore can't say whether it is realistic or not.) The bandwidth on the i820 is 1.6GB/sec, while the i840 is 3.2GB/sec. The difference is 1.6GB/sec. If cache lines are so long (perhaps they are including some look-ahead???), that it takes an i840 50ns to load one, then it would take the i820 100ns to load the same amount of data, thus accounting for the 50ns difference. That would give an effective cache line size of 1.6GB/sec * 100ns = 160 bytes. If the actual cache line is 128 bytes, this would account for most of the difference in latency. I have no idea what the actual cache line size is on the Coppermine, I'll try and look it up and post a note to this post, if I find it (and if my tiny 56K modem can download it). There is a relationship between bandwidth and latency, when reading in bursts. By the way, this is one of the issues that memory designers have to deal with. The classic problem with memory design is the tradeoff between burst length, bus utilization efficiency, and latency. Increasing burst length causes an increase in bus utilization efficiency (when you are switching directions between bursts) but also an unwanted increase in latency. RDRAM does provide a better solution for these problems, but it is not enough to pay for the other costs of the technology, in my opinion. When calculating this tradeoff, one has to know the probability of a read access being followed by a write access and vice-versa, as opposed to a write being followed by a write or a read by a read. DDR and SDRAM is perfectly efficient for writes followed by writes (assuming a reasonable minimum burst length, so you can hide activates). For reads followed by reads, it is perfectly efficient if the reads are from the same chip, less so if the reads are from different chips. It is all kind of complicated. -- Carl