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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Bilow who wrote (40461)	4/20/2000 7:30:00 AM
From: gnuman	Read Replies (1) \| Respond to of 93625

Micron PR, "Micron Tech to demo 3 DDR platforms at Winhec" micron.com

To: Bilow who wrote (40461)	4/20/2000 9:13:00 AM
From: SBHX	Read Replies (1) \| Respond to of 93625

Granularity losses from an AGP adapter fetching chunks of 256 bytes will not be 0, but I guess this must have been covered a zillion times? Guess what's the sweet spot SBA transfers all these adapters and their underlying algorithms are tuned to? :) Cache lines are 32 bytes only, but AGP PIPE# and SBA accesses can apparently go to 256 bytes. The micron and 840 comparison by inquest are interesting not only in that they show the deltas in normal 'heavier load' apps (eg : linpack & giant spreadsheet models), which are more dependent on random memory accesses than sequential. Even sequential rd/wr favour DDR except for 2048KB Rds where the 840 is marginally ahead. inqst.com In fact, I suspect the 2048KB wr on DDR is going to be penalized by the memory trashing effect of the PIII's cache-rd-on-wr-miss behaviour, as each 32byte cacheline victim has to be flushed and written out, generating a pagefault every cacheline, as it goes to this funky, flush-fetch sequence, rdram, on the other hand only has to do this 1/8 as often if it is able to buffer up the writes and write them out every 256 bytes. If we go to 2GB writes, I'd expect the rdram wr to pull ahead. :) With even 440ZX MBs overclocking the FSB today, std 133-FSB i815 with a geforce256-DDR (or better) will probably be at least competitive with a similar equipped i820. 6ns SDR are relatively cheap and 7ns are everywhere, so overclocking 815 to 150 or 160 should be well within margins if the MB vendor really wants to. The 820 and 840 on the other hand, probably will not tolerate tweaking of the clocks as well, if we look how close on edge :) a 2 rdram slot 820 is today wit RDR-800 and extrapolate that data. Not much margin on these rdr memory either. ------ Disclaimer - SbH is chatty person with no position on rmbs, please don't send goons to break my limbs, or destroy my puny assets.

To: Bilow who wrote (40461)	4/20/2000 1:11:00 PM
From: Tenchusatsu	Respond to of 93625

Carl, some comments: 1) As you already mentioned, cachelines on the P6 bus are 32 bytes long. AGP accesses can get pretty long, like up to 256 bytes per access, even longer when accesses to consecutive 256B blocks are pipelined. 2) I don't think Intel's bandwidth-vs-latency chart is assuming a lot of AGP activity. The chart would have made some sort of mention as to what AGP was doing in the meantime. And the Via PC133 chipsets would not be showing good latency from the beginning, considering how PC133 is not ideal for handling concurrent processor and AGP traffic. 3) My hunch is that most benchmarks out there right now hardly stress memory bandwidth, which is why Via's chipset looks so strong compared to Intel's 820 chipset. Anyway, I'll try and find out more on my side of the fence. Tenchusatsu