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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (107318)	4/22/2000 12:56:00 AM
From: Scumbria	Read Replies (6) \| Respond to of 1572921

Joe, 1. Do you find the cache hit rates they use in the ballpark? They have a hit rate of 128K L1 at 95%, additional 512K L2 at 80%, 256K at 78%, 64K at 65%. I would say that all of the hit rates are too low. A 128KB L1 hit rate should be >98%. There isn't any formula, and it is not consistent from application to application. I base my numbers on trace simulations. There was some talk on RMBS thread about the amount of time it takes to fill a cache line. How many bytes are in a cache line on Piii, Athlon? Does the CPU have to wait until the cache line is full, or can it start to use the data as it comes? Very good questions. I believe that the L1 caches of both Athlon and PIII have 32 byte line sizes. If not 32, then 64 bytes. The execution unit does not have to wait for the linefill. The critical word is always forwarded directly to the execution unit, and then the line is written into the cache when all the data is available. The number of clocks required for a linefill is small, and has minimal impact on performance. Some CPU's allow the linefill buffer to be snooped for subsequent data, before it is actually written into the cache. Scumbria

To: Joe NYC who wrote (107318)	4/22/2000 1:17:00 AM
From: Charles R	Read Replies (2) \| Respond to of 1572921

Joe, <1. Do you find the cache hit rates they use in the ballpark? They have a hit rate of 128K L1 at 95%, additional 512K L2 at 80%, 256K at 78%, 64K at 65%. What would be the hit rate of 32K L1 (Pentium), or let's say going from 256K L2 to 512K, 1MB, 2MB. Is there an easy to remember formula to get the hit rates?> The answer is it depends on the application. I used to have friend who had a hobby of writing programs that thrash the cache to bring some mainframes to a crawl. Chuck