Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: pgerassi who wrote (107363)	4/22/2000 1:16:00 PM
From: Scumbria	Read Replies (1) \| Respond to of 1585309

Pete, I don't necessarily agree with your assessment of the increased value of high associativity. Particularly your statement that a 64K fully associative will produce a higher hit rate than a 512K direct mapped. Can you provide more data? As to the power requirements, how is this any different than a ALU, FPU or Decoder? Every single clock cycle would require 1024 26 bit compares in both the data and instruction caches. These are followed by a 1024 bit "or" gate to generate the hit signal. The power and timing issues are overwhelming. How do you drive the address into 1024 comparators in a single clock? If you know how to do this and are looking for a new job, please send me your resume! Regards, Scumbria