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Technology Stocks : ADI: The SHARCs are circling! -- Ignore unavailable to you. Want to Upgrade?

To: Jim Oravetz who wrote (1658)	4/24/2000 7:17:00 PM
From: BostonView	Read Replies (2) \| Respond to of 2882

Can a techy comment on this? It sure sounds juicy. Apr. 21, 2000 (Electronic Engineering Times - CMP via COMTEX) -- NORWOOD, MASS. - Analog Devices Inc. will be first to use the "PulseDSP, " a customizable math processor array devised by startup Systolix Ltd. (Liverpool, England). Introduced at the DSP World Spring Conference, the array consists of 144 separate multiply/accumulate cells whose function is user-configurable. It will provide real-time digital filtering for the A/D converter Analog Devices plans to introduce later this year. The customizable processor array is said to outperform both FPGAs and general-purpose DSPs on communications, multimedia and other signal-processing tasks. PulseDSP consists of bit-serial multiply and adder cells that can be field-configured to operate in parallel. In Analog Devices' data converter, a version of its AD7723 16-bit sigma-delta A/D, the array serves as a programmable notch filter. The converter oversamples (at up to 20 MHz) to extract a clean 1.2-MHz signal. In this application, the PulseDSP array acts as a finite impulse response filter, said Gordon Work, Systolix' managing director. The PulseDSP-which provides about 130 million MACs to the standard A/D-allows the A/D to be programmed with ideal response characteristics, configuring its low-pass or bandpass frequencies and roll-off characteristics. The array can support communications applications-controlling filter coefficients, decimation ratio, interpolation, and output rates-processing signals up to 400 MHz, said Work. One example is a decimation filter for RF and IF circuits. The filter will be used to digitally extract a baseband signal from a higher-frequency carrier, he said. While the configuration of math processing elements in Analog Devices' converter would be either ROM-controlled or mask-programmable, it could be controlled by an EPROM (or an external microprocessor) in other applications. This "field-programmable processor array"-which Systolix calls FPPA-resembles an FPGA because of its flexibility and field programmability. Unlike FPGAs, the FPPA clocks at higher speeds and is optimized for math processing functions rather than general logic. Like a VLIW processor, the FPPA harnesses a massive amount of parallel processing resources. The difference is that the math processing resources reflect a smaller level of granularity and are hardwired like programmable logic blocks instead of controlled by a very long instruction word. In this way, hundreds-even thousands-of multiply-accumulate cells can operate simultaneously at video speeds, said Gareth Jones, Systolix' technical marketing manager. This allows up to 10 billion 16-bit MACs per second to be drawn from a 5 x 5-mm, 0.35-micron CMOS die, he said. Systolix believes the technology will spawn families of stand-alone digital filters, as well as custom chip designs. BV