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To: Tenchusatsu who wrote (41098)	4/27/2000 11:19:00 PM
From: jim kelley	Respond to of 93625

Fair enuff ...A lot of the technical discussion on this thread has been too simple minded and agenda oriented to actually get at the heart of the bandwidth and latency issues. I think the Toshiba article helps show that the bandwidth and latency issues deserve a more thorough analysis at the memory architectural level. The article on the inadequacy of the benchmarks currently being used seems to show that INTEL has thought this matter through more deeply than most of us knew. This is also shows that the best choice of memory architecture depends on the computational environment being targeted and this is not done best with old linear benchmarks. JK

To: Tenchusatsu who wrote (41098)	4/28/2000 7:58:00 AM
From: gnuman	Read Replies (1) \| Respond to of 93625

Tench, re: Benchmarks. This whole issue is murky and highly politicized. It appears the makers can develop benchmarks that highly favor their own designs and disparage the competition. There are many examples of this throughout the years. I suspect that a DDR company could write a maximum sustainable bandwidth BM that invokes the temperature sensor and slows down the clock on RIMM's. But would this be representative of real world conditions? I doubt it. I personally have little faith in maker derived BM's. (Mostly based on experience). I would like to see the industry and press agree on an industry standard set of BM's that de-politicizes the whole issue. JMHO's