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To: Captain Kirk who wrote (41182)4/30/2000 12:14:00 PM
From: jim kelley  Respond to of 93625
 
Captain Kirk

I do not have confirmation. This is the first article I have seen that said that AMD was using the EV6 and EV7 bus interfaces from DEC.

It makes sense for an EV7 to be using 8 RDRAM channels.
RDRAM has a higher page hit ratio with its 32 banks of dram than DDR has with its 16. Thus the maximum bandwidth of the DDR DRAM needs to be multiplied by .75 to obtain the maximum sustainable bandwidth. For RDRAM the the multiplier is .93. This is the "hidden latency penalty" incurred in the DDR architecture. Also, the clock rates scale better with the RDRAM packaging and they can match the clock rates to the 400 MHZ front side bus on Willamette. Finally, the PCB layout and manufacturing is simpler for RDRAM with its narrower busses.

The DDR she can't take anymore Captain...

Scotty