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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (108597)	4/30/2000 12:56:00 PM
From: Dan3	Read Replies (1) \| Respond to of 1571216

More on Quad Data Rate.... Here is a case where concurrent reads and writes to individual bytes are considered to double the data rate. Note that while total throughput of the bus is still DDR, if the CPU is waiting for two non-contiguous bytes or words, this would have the effect of doubling the throughput of the bus. Perhaps this is what Intel is up to. Dan xilinx.com Each QDR SRAM has separate control signals for the read and write ports, while the address and data ports are common for all the SRAMs. The controller supports concurrent double data rate (DDR) operations on all of the input and output signals and allows byte-write operations into the memory. Operating in the single-clock mode the controller significantly simplifies the memory interface. "Xilinx is the first semiconductor company to deliver a QDR SRAM memory controller solution. We are very pleased to be working with the QDR SRAM consortium in creating next-generation high performance solutions," said Kapil Shankar, senior marketing director for the High-volume Business Unit at Xilinx. "This Spartan-II reference design further extends our leadership role in providing cost-effective solutions for a wide range of applications." "The QDR SRAM consortium is pleased to work closely with Xilinx in providing a Spartan-II FPGA based high-performance, cost-effective memory controller solution," said Matthew Arcoleo, strategic marketing manager for the Memory Products Division at Cypress Semiconductor. "The availability of a free memory controller reference design will proliferate the use of QDR SRAM based networking solutions."