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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (108715)	4/30/2000 11:48:00 PM
From: Dan3	Respond to of 1571911

Re: So the CPU reads the voltage on the data lines 4 times in the cycle and that's how it get's the data... Hi Joe, Could very well be. Regards, Dan

To: Joe NYC who wrote (108715)	5/1/2000 10:15:00 AM
From: milo_morai	Respond to of 1571911

Jozef for Synchronous data your statement is not correct. " You have a clock that generates a signal: Clock Waveform _ _ _ \| \|_\| \|_\| \| 1234567890 Now, the CPU has the data lines, that are basically just connections to the outside world that can be at high or low voltage. Suppose you are trying to communicate data string 1011. The voltage on the data line would be Standard clock Data Waveform ____ _ \|___\| 1234567890 DDRate Data Waveform _ _ _ \|_\| \|_\| \| 1234567890" Data is sync'd on the rising or falling of the clock and it doesn't matter if your sending all zeros all ones etc. Data can only change state on the rise or fall of the clock. 1,5 and 9 are rising data can change logical state. or when 3,7 and what would be 11 are falling. now if your using DDR your data can change state on the rise and the fall of the clock so data is transmitted 1,3,5,& 7 That has always been my understanding of Synchronous data. Milo