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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (108726)	5/1/2000 12:06:00 AM
From: Bilow	Respond to of 1572134

Hi Dan3; Re QDR system, engineering difficulty of clock versus data. You are correct, the clock runs slower than the data. That means that some things on the data bus will be worse, in particular FCC type emissions. On the other hand, data buses only have to be valid at the time that they are sampling, while clocks have to be valid all the time. So the problem with the clock basically means maintaining a jitter limit on the derived PllClk (i.e. noise on the clock will get added to the DLL jitter, but noise on the data lines only shows up on that data line). So the engineer might route the data lines without regard to crosstalk, but make very sure that the clock lines are very carefully ran. For that reason, it might be likely that the power consumed by the clock line is well in excess of the power consumed by a data line, assuming that they are running the same frequency. But the information carried by the clock line is only relative timing, and you can get that back with a DLL or PLL. Its basically that improving the clock lines also improves the performance of every flip-flop they attach to. But improving a data line only helps that one data line. This applies regardless of the 1x, 2x, or 4x clock multiplying scheme. And as soon as you decide to build a DLL for the clock, why not make it a 4x? They're almost as tight as the 2x or 1x versions. The result: You automatically reduce the FCC emissions and power consumption of the clock lines without reducing performance by anything significant. -- Carl