ah, the Ganges (Padma). believe it or not, i played in the rice paddies of Dhaka, nee Dacca, as a wee lad: u.s. state department brat.
i once told a friend from Delhi that i lived in Bangladesh. his reply: "i'm so sorry you for."
for something more substantive ...
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Electronic Engineering Times
May 15, 2000, Issue: 1113
Section: Semiconductors
Three roll high-layer processors for Sonet
Loring Wirbel
techweb.com
LAS VEGAS - Three physical-layer IC players that recently swallowed up digital packet-processing specialists came to the NetWorld+Interop show here last week with new Sonet chip offerings combining the best of their merged talents.
Vitesse Semiconductor Corp. (Camarillo, Calif.) announced it is about to sample an OC-192 traffic management engine called PaceMaker, developed by the North Carolina packet-classifier company Orologic, which Vitesse acquired in March.
Applied Microcircuits Corp. (San Diego) debuted the latest of its "rivers" processor family from the former Cimaron Communications Inc. Only weeks after launching the Indus framer chip, AMCC came to NetWorld+Interop with Ganges, an OC-192 framer that can handle either channelized or concatenated Sonet traffic.
Conexant Systems (Newport Beach, Calif.), meanwhile, introduced new broadband multiplexer and synchronous communication control chips, bringing together its own Sonet expertise with the packet-processing capabilities it acquired from Maker Communications Inc. The so-called BAM and MUSYCC chips are intended to be used with Conexant's OptiPHY framer and multiplexer for 155- and 622-Mbit Sonet rates.
All three companies are seeking to fill missing slots in order to offer end-to-end communication families at a variety of Sonet rates, stretching from the physical layer to Layer 3 routing. They will be challenging such established architectures as PMC-Sierra Inc.'s Saturn/User Network Interface (S/UNI) family, upgraded here last week to 2.48-Gbit At Vitesse, the PaceMaker 2.4 is intended to provide a full suite of quality-of-service features for both Internet Protocol (IP) packets and asynchronous transfer mode cells at OC-48 data rates. Its embedded ATM segmentation-and-reassembly engine can handle up to 256,000 independent sessions.
The PaceMaker can be used in conjunction with programmable parsing devices that Vitesse is offering through other acquisitions, such as the TeraPower processor from the former Xaqti Corp. and the Prism family from Sitera Inc., which Vitesse is in the midst of acquiring. PaceMaker is said to be the first traffic manager to support Earliest Deadline First scheduling algorithms in silicon.
Designs are under way to upgrade the PaceMaker to an OC-192 version, to handle traffic at full 10-Gbit/second data rates. Concurrent with the higher-speed PaceMaker, the Orologic group at Vitesse also will offer Monitor 4.8 Operations Administration and Maintenance engines for ATM, sampled in both 2.5- and 10-Gbit versions.
PaceMaker 2.4 for OC-48 networks will sample in June in a 756-pin ABGA, priced at $1,095 each in sample quantities.
For its part, the Ganges S19202, the latest from the AMCC Cimaron group, is an OC-192 framer that supports full-duplex mapping of both ATM cells and packet-over-Sonet IP packets, in either concatenated or channelized Sonet payloads. In concatenated mode, the chip can support a single OC-192c or four OC-48c interfaces. It can support channels of any granularity and combination, adding up to a single OC-192 interface or four OC-48 interfaces-up to 16 separate STS-12 payloads.
Rides FlexBus-4
Several terabit-router OEMs took part in product definition for Ganges, to optimize the chip for handling bursty concatenated traffic in Internet backbones. The same chip can transmit 10-Gbit Ethernet packets by using the FlexBus-4 interface, which links packet-over-Sonet and ATM traffic to the Optical Interoperability Forum's SPI-4 interface. A direct-map mode on the chip allows any type of traffic, including Gigabit Ethernet, to be mapped directly into a Sonet payload envelope.
Ganges implements a Sonet automatic-protection switching port in hardware, so that Sonet failover APS rates of less than 50 milliseconds can be supported with any type of traffic. Packaged in a 624-pin ball grid array, the chip is priced at $725 in quantities of 1,000.
Conexant's BAM and MUSYCC devices are intended for channelization of Sonet pipes down to lower, time-division multiplexed rates. The BAM is a general-purpose mux/demux, mapping and framing device that can combine three DS-3/E3 inputs into any combination of 84 DS1 (T1) or 63 E1 circuits. The chip generates and terminates all virtual-tributary and virtual-container path overheads, supporting Sonet-to-PDH mapping at rates of 51 Mbits/s, 2 Mbits/s and 1 Mbit/s.
It includes three DS3/E3 framers, three M13/E13 mux/demux blocks and 84 embedded DS1 framers, along with 63 embedded E1 framers. The CS29503 BAM, packaged in a 31 x 31 SBGA, is priced at $790 each in volumes of 10,000.
The companion MUSYCC-1024 device is a multichannel High-level Data Link Control processor that formats and deformats up to 1,024 HDLC channels. The chip supports 32 serial ports with an aggregate full-duplex throughput of 500 Mbits/s. In a typical application where OC-12 traffic must be channelized to DS1 or E1 rates, four BAM devices, two MUSYCC devices and a single OptiPHY-M622 chip would constitute the full channelization solution.
The MUSYCC CX28500 controller is packaged in a 35 x 35 SBGA, priced at $275 each in quantities of 10,000. |
