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To: Bilow who wrote (41375)	5/5/2000 4:37:00 AM
From: Tenchusatsu	Read Replies (1) \| Respond to of 93625

Carl, <Basically, the chipset will automatically group together write accesses so that they all occur at once, instead of being split up among the reads. That way, the bus has to be turned around far less often.> What you are talking about is write-buffering, and it's not just something that benefits DDR, it also helps RDRAM as well. No matter what the turn-around latency is, you want those reads to return data in the shortest amount of time possible. Mixing in writes among the reads is a sure way to impact performance, even with quick turn-arounds. There are still other causes of dead cycles besides those caused by read-to-write transitions. Bank-aliasing is a nasty one, but at least in servers, multiple DDR channels are interleaved in a way that minimizes bank-aliasing. Desktops, however, are a different story. With only one channel, you can bet bank-aliasing will impact performance in a loaded system. (And if the memory subsystem is hardly loaded, then DDR wouldn't be necessary, and PC133 should suffice.) Tenchusatsu