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To: jim kelley who wrote (41728)5/8/2000 8:56:00 PM
From: cellhigh  Read Replies (1) | Respond to of 93625
 
fwiw rmbs was asking 195 on my ecn at the close.



To: jim kelley who wrote (41728)5/8/2000 10:09:00 PM
From: milo_morai  Respond to of 93625
 
DDR SDRAM

The Hyundai DDR SDRAM family is high speed Double Data Rate(DDR) Synchronous DRAM's fabricated with the Hyundai high performance CMOS process. While all address and control inputs are latched on the rising and falling edge of the clock(falling edge of the /clock), data, data strobe and data mask inputs are sampled on both rising and falling edge of the clock. The data path is internally pipelined and 2-bit prefetched to achieve higher bandwidth. Because data rate is doubled through reading and writing at both rising and falling edge of the clock, 2X higher data bandwidth can be achieved




64Mbit Org.
Bank
Ref.
Part No.
I/O Interface
Max.(MHz)
Package
Remark

16Mx4
4
4K
HY5DV654022TC
SSTL_2
133/125/100
400mil 66pin TSOP-II


8Mx8
4
4K
HY5DV658022TC
SSTL_2
133/125/100
400mil 66pin TSOP-II


4Mx16
4
4K
HY5DV651622T
SSTL_2
183/166/143
400mil 66pin TSOP-II


2Mx32
4
2K
HY5DU663222T
SSTL_2
183/166/143
100pin TQFP





128Mbit Org.
Bank
Ref.
Old Part No.
New Part No.
I/O Interface
Max.(MHz)
Package
Avail.

32Mx4
4
4K
HY5DU1294022TC
HY5DU28422T
SSTL_2
133/125/100

(PC266/200)
400mil 66pin TSOP-II
Now

16Mx8
4
4K
HY5DU1298022TC
HY5DU28822T
SSTL_2
133/125/100

(PC266/200)
400mil 66pin TSOP-II
Now

8Mx16
4
4K
HY5DU1291622TC
HY5DU281622T
SSTL_2
133/125/100

(PC266/200)
400mil 66pin TSOP-II
Now




Device Operation

- 64M DDR SDRAM functionality description(Preliminary)

- 128M DDR SDRAM functionality description(Preliminary)



DDR SDRAM Module : 128Mb DDR SDRAM Based

- 184pin Unbuffered DIMM



- 184pin Registered DIMM



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