Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Gopher Broke who wrote (111665)	5/20/2000 9:18:00 AM
From: porn_start878	Read Replies (1) \| Respond to of 1572873

Gopher Broke <I was just browsing the AMD presentation at the DDR conference and in the chipset section they place a lot of emphasis on the matching of bus speeds either side of the northbridge giving "significant benefits". > It remind me a big question my dad was bothered 3 or 4 mounts ago. It was about PC133 and the 200 bus EV6. He was talking about "phase djetting" or something like that. Does the KX133 buffer ahead the next word coming from memory to reduce phase discrepancy between CPU and PC133? If so, it will induce latency. To explain it more in detail: Let T be the time when the first word arrived at the CPU and tic200 be the time between each tic of the clock on the EV6 bus while tic133 is for the clocking of the PC133. At T+tic200 the CPU is ready for the next word but the PC133 is not ready before T+tic133 so the CPU will have to wait on the next tic200 before reading the next word. This will result in reading succeeding word every 2 tic200 giving a throughput equal of the PC100 throughput. Since Bench show a better result for PC133 memory to CPU transfer, there must be a tricky way of avoiding this "phase djeter". Can anybody could give a clue? max