Rambus will present 1.6Gbits/s per pin June 15-17, 2000.
Rambus announced Dec. 10, 1999: eoenabled.com
"We plan to double the data rate of our fastest chips from 800 MHz per pin to 1.6 GHz," said Geoff Tate, Rambus' chief executive officer. "We already have the faster technology working in a lab setting as an engineering demo, and we expect to see product announcements by the second half of next year."
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SOI debate an expected high point at twin VLSI conferences -- IBM says yea,Intel nay, to silicon-on-insulator
Sat May 20 00:00:00 EDT 2000
May. 19, 2000 (Electronic Engineering Times - CMP via COMTEX) -- AUSTIN, TEXAS -
Sharply differing views of the role silicon-on-insulator technology will play in
the semiconductor industry will be among the issues taking center stage at next
month's VLSI Technology and VLSI Circuits symposia. The linked conferences will
run back to back June 13-17 in Honolulu (www.vlsisymposium.org).
At the VLSI Technology Symposium, IBM Microelectronics will detail two
130-nanometer (0.13-micron) processes: one in conventional bulk silicon and a
second based on silicon-on-insulator (SOI) wafers.
In rebuttal, Intel Corp. researchers will argue that for the 100-nm (0.1-micron)
generation, devices fabricated in SOI have "significantly diminished performance
gain relative to bulk CMOS," according to an abstract of their paper.
The Intel group, from the company's Portland (Ore.) Development Center, will
argue that any performance gains achieved with the higher-cost SOI technology at
the 180-nm generation will diminish as scaling progresses to 100-nm gate lengths
and beyond.
Intel Fellow Mark Bohr has contended that the extra cost of SOI wafers makes the
approach impractical for volume manufacturers such as Intel. The company's VLSI
paper takes a technical bent, claiming that a problem known as the history
effect slows performance at deep-submicron dimensions.
IBM clearly thinks otherwise. Its Microelectronics Division is engaged in a
massive shift toward SOI wafers, starting with performance-critical processors
and moving out to system-on-chip (SoC) applications.
At the technology symposium, a team based at IBM's Semiconductor Research and
Development Center (Hopewell Junction, N.Y.) will describe a 1.2-volt SOI
process at 130-nm design rules, using 248-nm lithography. The technology
includes eight levels of copper interconnect, a local interconnect that uses a
tungsten damascene approach and an advanced low-k interlevel dielectric,
previously described as the SiLK organic material. The IBM team will claim to
have the "densest six-transistor SRAM reported to date," with a cell area of
2.16 square microns.
Another team from the same IBM R&D center will describe modeling work of SOI
circuits that contributed to a Power-PC design that runs at 660 MHz, one of
IBM's initial success stories in working with SOI technology at the 180-nm
generation.
IBM presented a gigahertz embedded-DRAM technology at last February's
International Solid State Circuits Conference (ISSCC), but that was implemented
in bulk CMOS. Because of the so-called floating-body effect, implementing any
memory circuit in an SOI technology has been challenging, though it has been
done.
Meanwhile, another group from IBM will describe a merged bulk DRAM and SOI logic
technology, using patterned SOI at the 0.25-micron generation. The abstract of
the paper states that IBM for the first time has fabricated commodity 64-Mbit
DRAMs, and logic device and circuits, on patterned SOI wafers. The company says
it used a Simox technology to implant the insulation layer, and apparently has
developed a means of selectively implanting SOI regions alongside bulk silicon
to enable an SOI-based embedded DRAM.
Also in Hawaii, Mitsubishi Electric, which has offered commercial SOI devices
for several years, will describe a 180-nm SOI technology and discuss the
implications for applications that need embedded RF and analog circuitry.
While IBM tries to gain a performance edge with SOI and silicon germanium
technologies, it will be offering a cost-effective 130-nm bulk CMOS process to
the commercial ASIC and ASSP marketplace. At the technology symposium, a team
from IBM Microelectronics and Infineon Technologies Corp. will describe the
130-nm process they are jointly developing at Hopewell Junction.
IBM and Infineon invited UMC Corp. (Hsinchu, Taiwan) to join them in developing
a common technology at 130-nm and 100-nm design rules for ASIC and foundry
customers. That process at the 130-nm generation includes a modular triple-gate
oxide concept. By varying the oxide, different levels of performance and current
leakage can be offered to customers for SoC applications.
The bulk 130-nm process, which the trio plans to introduce later this year, will
include a deep-trench-based embedded-DRAM technology and seven levels of copper
interconnect with a low-k dielectric between the metal. The IBM-Infineon team
also will describe how optical enhancement techniques can be used to push 248-nm
lithography to 130-nm design rules. The 6T SRAM cell size for the process is
rated at 2.48 square microns, larger than the SOI-based cell.
Process platform
Elsewhere at the conference, Toshiba Corp. researchers will present a 130-nm
process platform optimized for SoC applications, and Taiwan Semiconductor
Manufacturing Co. will detail its 150-nm process.
Motorola Inc.'s DigitalDNA laboratory will send a team to Honolulu to describe a
180-nm process optimized for low-power, low-cost consumer wireless products.
Motorola has adopted a superhalo implantation approach to integrate the
higher-voltage I/O circuits with a much thicker gate oxide. The I/O transistors
could be fabricated alongside the low-leakage devices with three fewer mask
layers than a conventional approach, the company said.
Wah Kit Loh, a Texas Instruments Inc. engineer who is on the organizing
committee for the VLSI Circuits Symposium, said the trend toward high-speed ICs
aimed at the communications space "is the focus of a lot of papers at this
year's meeting, and by that I mean dealing with the signal both on and off the
chip." A paper from MIT, for example, will present methods of on-chip
measurements of picosecond signals. That's an essential starting point, since
"simply measuring picosecond signals has become difficult," Loh noted.
Distributing the clock signal over different edges of the chip, and creating the
phase-locked loop circuits needed for high-speed ICs, will be central to the
discussions at the conference, said TI engineer David Scott, program chairman
for the circuits event.
At the VLSI Circuits Conference, Toshiba researchers will present work on how to
minimize the subthreshold leakage in memory circuits fabricated with 100-nm
technology. "As the transistors get smaller, the subthreshold leakage becomes a
really difficult problem," said Scott. "As you put as many as 256 bits on a
single bit line, it becomes really difficult to tell which bits are turned on as
other bits leak current." Toshiba has "come up with techniques to minimize the
problem."
Bandwidth has become a differentiator in the memory business. Samsung will
present a 288-Mbit packet-based DRAM with a bandwidth rating of 2 Gbytes/second.
And Rambus Inc. will present its next-generation technology, which claims to
reach a transfer rate of 1.6 Gbits/s per pin. That would essentially double what
Rambus is delivering today on a per-pin basis.
Scott said several papers will detail pulse amplitude modulation techniques.
Sending signals of different amplitude over two separate wires can yield high
data transfer rates, he said. That is particularly important for digital
subscriber line chips that attempt to achieve higher data rates than the copper
phone wiring was designed to support.
To that end, a short course on wireline and optical-fiber IC design will precede
the VLSI Circuits Symposium. It was organized by Dick Hester, who has managed
ADSL design teams at Texas Instruments, and Sailesh Rao of Level One, an Intel
subsidiary.
Quality rival
Though slightly smaller, the VLSI meetings attract a range and quality of
presentations that rival the two other major semiconductor technology meetings:
the ISSCC, held in February, and the International Electron Devices Meeting
(IEDM), held in December.
In recent years the VLSI meetings-with the technology event focused on R&D and
the circuits conference on implementation issues-have alternated between Kyoto,
Japan, and Honolulu. The 2000 event maintains a rough balance between papers
from companies based in Asia and the West.
Following a workshop on Sunday, June 11, on statistical metrology, the VLSI
Technology Symposium kicks off on June 12 with a short course on the key
technologies for 130- to 100-nm process generations, organized by Simon Wong of
Stanford University and Seiichiro Kawamura of Fujitsu Ltd. The course will
include presentations by various corporate technologists on the major process
challenges in lithography, interconnect, the gate stack and shallow junction
processes, and design issues.
The technology symposium runs from Tuesday through Thursday. The VLSI Circuits
Symposium overlaps it by one day, running from Thursday, June 15, through June
17.
Rump (evening) sessions include a look at the circuit and systems technology
that might prevail in 10 years, including projections about the future of the PC
and the place of SoC designs. Other sessions will ponder the limits to DRAM
scaling; optical vs. nonoptical lithography, and novel structures and processes
that will allow continued MOSFET scaling.
Betty Prince, a consultant who specializes in embedded DRAM, will moderate a
panel on that technology featuring speakers from companies that have tried-and
in some cases, failed-to realize its promise.
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