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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (111742)	5/21/2000 6:36:00 PM
From: Scumbria	Respond to of 1583934

Elmer, With increased on-die L2 is memory bandwidth as all important as it used to be? The fewer the frequency of cache misses, the lower the bandwidth requirements. The counteracting factor is of course clock speed. At greater clock speeds, the greater the frequency of cache misses. The miss rate can only be decreased so much by increasing the cache size, but the clock frequency has several orders of magnitude headroom. At some point, the model will have to switch over to multiple CPUs with very large caches and embedded DRAM. At that point maybe we can lose all this DDR and DRDRAM nonsense. Scumbria