Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: gnuman who wrote (42855)	5/23/2000 9:03:00 AM
From: Scumbria	Respond to of 93625

Gene, Can you have all three simultaneously? (Low power, maximum page hit's and low latency). No. The core technology is identical in DDR and DRDRAM. Power savings comes from turning things off. Turning them on requires time, which means increased latency. Scumbria

To: gnuman who wrote (42855)	5/23/2000 9:14:00 AM
From: Ian Anderson	Read Replies (1) \| Respond to of 93625

Gene, I don't know if you want to hear this, but lets try >If a RIMM dissipates half the power of a DIMM, why is there a heat spreader? To spread the heat! When you read a cache line (64 bits)from SDRAM the data comes from 8 chips, each of which takes current both internally, and to drive the external load on its output pins. The heat generated is spread evenly over the DIMM. When you read 64 bits from a RIMM it will typically all come from the one RDRAM, and only that one heats up. Because access is typically not random there is a risk that the application will repeatedly access the same RDRAM while all the others are cold. Hence the need to average out with the heat spreader. >I've seen references to a heat warning label on the spreader. Is that true? I've never seen one (on any Samsung RIMM) >Are the chips periodically monitored for temperature and calibrated to adjust ICC? Yes there is monitoring, but it is mostly used to control the drive current on the output pins. >When many chips are in active power mode can the clock be automatically adjusted lower to reduce temperature? Almost, the clock speed is kept constant, but access is only allowed in shorter bursts. I never saw evidence in a real life application of this protection mechanism kicking in >What are the latency impacts of switching between power modes? Read the data sheet? Ian