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To: wily who wrote (103691)5/26/2000 1:27:00 PM
From: wily  Respond to of 186894
 
Food for thought (based on a 1/4" X 1/4" memory area,
where cell size = F*L^2). Also, note that Samsung is
already in limited production @ .12um:

   
L F cell size cells Mcells Mbits/chip Gbytes per computer
(um^2) per um^2 per chip @ 3bits/cell @ 3 DIMMs per mobo
& 16 chips per DIMM
.25 12 0.75 1.33 53.7
.18 12 .389 2.57 103
.18 6 .194 5.14 207 621 3.7
.18 4 .130 7.72 311 933 5.6
.18 2 .0648 15.4 622 1866 11.2
.12 6 .0864 11.6 466 1400 8.4
.12 4 .0576 17.4 700 2100 12.6
.12 2 .0288 34.7 1400 4200 25.2


If the cache area on a cumine is 20mm^2, then at F=4
and L=.12um (not too far off, IMO), you could fit
43MBytes (129MBytes w/3bits/cell) of OUM on the die.

wily



To: wily who wrote (103691)5/26/2000 1:33:00 PM
From: Tenchusatsu  Read Replies (1) | Respond to of 186894
 
Wily, <Would you like some logic with that memory?>

You took my quote related to the new Xeon w/ on-die cache (a.k.a. Cascades)! Mine goes something like this, "Would you like a processor to go with that SRAM array?"

Tenchusatsu