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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (43169)	5/30/2000 3:17:00 AM
From: Joe NYC	Read Replies (1) \| Respond to of 93625

Tenchusatsu, anti-Rambus coalition, who can then turn the word "latency" into a political buzzword. Like most FUD, it contains a grain of truth and a pound of bull. In that case, if the latency is only a grain of truth and a pound of bull, why does Intel and AMD create more and more elaborate caching schemes? Why does inferior P6 core with low latency L1 and L2 beat superior K7 core with higher latency L1 and L2? Latency is in fact the key to performance, bandwidth is only a side show. I think the place where bandwidth makes some difference are servers, especially multiple-CPU servers. Let's see how well Rambus does there. Unfortunately, most real-world benchmarks these days do not exercise peak bandwidth. If the peak bandwidth is not the performance bottleneck, why throw your limited dollars fighting something that is not a problem? Doesn't it make more sense to look where the bottleneck is and apply your dollars there, in order to achieve better performance? If you have a budget to build a computer, and you want to build a fastest performing computer with this amount of money. Suppose you decide to spend $400 on Rambus memory. Now you have $300 less to spend on other components. You will end up with slower CPU, slower and smaller hard disk, less memory. Essentially, using RDRAM in a computer cripples the performance. Don't you find it disturbing as an Intel employee and shareholder, that for every system that is sold with RDRAM, Intel could have had up to $300 more in revenue had the buyer opted for SDRAM and faster CPU? Joe

To: Tenchusatsu who wrote (43169)	5/30/2000 9:43:00 AM
From: Scumbria	Respond to of 93625

Ten, Unfortunately, most real-world benchmarks these days do not exercise peak bandwidth. This may be due to the P6 bus not running fast enough, among other factors. As I have been pointing out for the last two years on SI, single processor systems generally don't require a huge amount of bandwidth from DRAM. Large on-board caches absorb most of the memory bandwidth requirements. As clock speeds increase, the total memory bandwidth requirement increases as well, but larger caches are again mitigating the bandwidth requirements to DRAM. It won't be too much longer before CPUs start using embedded DRAM to reduce off-chip DRAM utilization. This is already being used in PS2. There is no point complaining about benchmarks. The PIII bus has a peak bandwidth utilization of 800 MB/s, which cheap SDRAM can service quite adequately (as can be seen in Tom's BX-133 testing.) Scumbria