Fujitsu goes to .11 micron.........
eetimes.com
Fujitsu charts new course in flash after DRAM debacle
By Brian Fuller
EE Times
(06/01/00, 9:46 a.m. EST)
SANTA CLARA, Calif. ( ChipWire) -- During a briefing for analysts and
the press here, Fujitsu Microelectronics Inc. (FMI) executives charted
a bold course for the once-battered company, with lavish capital
expenditures to pay for the company's hoped-for dominance in flash
memory and its new 0.11-micron (drawn) process technology (see
May 31 story).
The vision was served up at the company's annual luncheon for press
and analysts on Wednesday, one year after FMI managers appeared
weary and defeated in the trough of the DRAM recession.
"Business is definitely good," chairman, president and chief executive
Ryusuke Hoshikawa said in an interview. "We're investing in many
areas and using our SOC technology to find customers in LAN, wireless
and set-top box areas."
Hoshikawa said Fujitsu Ltd., FMI's Tokyo-based parent, has budgeted
$4.6 billion for capital expenditures this year, 53% of which are going
to the Electronic Devices Group (EDG). That's a sector that this year
is forecast to deliver just 14% of the corporate parent's net sales.
That 53% figure is the highest percentage EDG has gotten since at
least fiscal 1996.
Half of that capital investment for EDG will fund ambitious flash
expansions, including a new line at the company's FASL joint-venture
fab operation with Advanced Micro Devices Inc. in Aizu-Wakamatsu,
Japan. The company also is converting its Gresham, Ore., fab almost
entirely to flash production, with 30,000 wafers per month expected in
the coming years. The new line at Aizu-Wakamatsu also is targeted
for 30,000 wafers per month. Analysts have estimated that FASL
produces almost one of every three flash devices in the world,
according to John McElroy, vice president of marketing and strategic
relations.
The other half of the EDG's capital plans will pay for SOC logic
expansion in existing quarter-micron and 0.18-micron capacity,
Hoshikawa said.
On the logic side, the new Cx90 0.11-micron process will hit customer
sites next year and deliver copper interconnects and up to 8 levels of
metallization. The process, with an eye toward high-speed
telecommunications, will incorporate mixed-signal and analog
functions, multi-level i/o and embedded DRAM.
Indeed that was the only context in which the word "DRAM" was
uttered at the briefing. In luncheons past, half the time was spent on
commodity DRAM product-mix strategies and pricing and capacity
considerations. A little over a year ago, however, in the depths of the
DRAM depression, FMI officials pulled the plug, backing away from
commodity DRAMs and focusing on flash and a special fast-cycle RAM
(FCRAM) architecture the company has developed.
While the DRAM business has rebounded, it hasn't swayed FMI officials
from jumping back in the pool; officials are turning away customers
that are asking them to rejoin the DRAM market.
Sticking to its guns on DRAMs apparently isn't hurting FMI: the
company expects to grow 35% in fiscal year 2000, ending March 31,
2001, outpacing the growth that many forecast for the semiconductor
industry as a whole this year.
More.......
semibiznews.com
Fujitsu bows 0.11-micron, all copper process,
targeting high-speed/low-power apps
Semiconductor Business News
(05/31/00, 06:35:30 PM EDT)
SAN JOSE -- Fujitsu Microelectronics Inc. today introduced its 0.11-micron
gate-length ASIC process capability, which it said offers the lowest power in the
industry, and uses an all-copper interconnect process.
The 0.11-micron technology (0.07 micron L-effective) will be available by the third
quarter of 2001.
Other features include shallow trench isolation, chemical-mechanical polishing
(CMP), and cobalt silicide (CoSi2) in transistor gate and source/drain. The
copper-interconnect process uses five to eight levels of metal and low-k dielectric
techniques with a k constant of 2.6.
Initial products developed using this process will support devices with as many as
56 million gates per chip. The gates will be characterized at 0.85 to 1.65 volt, with
analog and I/O blocks to be available in both 2.5 and 3.3 V. Densities are twice
those of ASICs manufactured using Fujitsu's 0.18-micron process technology, the
company said.
"This very deep-submicron technology continues Fujitsu's leadership in one of the
technologies driving advanced networking and communications design, as well as
digital A/V design," said Ryusuke Hoshikawa, Fujitsu Microelectronics' president
and CEO.
"The new ASIC series and technology provide our customers with extremely fast,
high-density products with very high pin counts, along with a large array of cell
libraries, macros and IP cores. We will be moving aggressively to bring our initial
products to our leading customers in Japan and in North America quickly and
efficiently," Hoshikawa added.
Fujitsu's first release will be the high density, low power Standard Cell CS91 and
the quick TAT (Turn Around Time) Embedded Array CE91 ASIC series designed
for high density, highpin count LSI and portable system LSI. Fujitsu also plans an
embedded DRAM offering, the CS90DLS, which will provide more than 192
megabits of DRAM for each 100 mm2 area.
Clock frequencies for the embedded DRAM will reach 200 MHz for SDRAM and
more than 300 MHz for Fujitsu's FCRAMs (Fast Cycle RAMs). Packaging for the
CS91/CE91 series will be in high ball-count and fine ball-pitch flip-chip BGAs. |
