Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : General Lithography -- Ignore unavailable to you. Want to Upgrade?

To: Jim Oravetz who wrote (1239)	5/31/2000 12:51:00 PM
From: Jim Oravetz	Respond to of 1305

SAN JOSE, Calif.--(BW)--May 31, 2000--Numerical Technologies, Inc. (Nasdaq:NMTC) today announced the successful fabrication of the world's first 25 nm transistor gates produced entirely by optical lithography. The 25 nm (0.025 micron) transistor gates on the integrated circuit (IC) were achieved using Numerical's patented phase-shifting technology and DUV 248 nm optical lithography. This achievement marks the first time 248 nm lithography equipment has produced a 25 nm transistor gates. This achievement comes three months after a February release announcing the first 50 nm transistor gates to be manufactured with optical lithography. The 25 nm gates represent some of the smallest gates ever patterned by conventional optical lithography. This result also demonstrates the potential for existing optical lithography tools to generate feature sizes significantly smaller than originally anticipated. "The fabrication of 25 nm gates is a dramatic step forward from our February announcement that 50nm transistors had been manufactured using our technology," stated Y. C. (Buno) Pati, CEO of Numerical Technologies. "With Numerical Technologies' phase shifting, optical lithography will no longer be the limiting factor in advancing integrated circuits." Previous estimates have held that alternative lithography or 157 nm lithography techniques would be required to print lines at 70 nm, and industry sources agree that these techniques may not be available for seven to 10 years. Research Results to be Discussed At 3-Beam Conference Technical details of the results and methods used to fabricate the device will be presented at the 44th International Conference on Electron, Ion, and Photon Beam Technology & Nanofabrication (IEDM 3-Beam Conference) currently taking place in Palm Springs, California. Dr. Michael Fritze, et al. of MIT Lincoln Laboratory is scheduled to present a technical paper describing the results, titled "Sub-100 nm SOI CMOS by DUV Optical Lithography," on Wednesday, May 31 at 1:50 pm. Previous Successes With Phase Shifting The latest achievement is another success for subwavelength design and manufacturing. In February, at the SPIE 2000 symposium, Dr. Fritze delivered a paper that described the successful fabrication of 50 nm transistors using Numerical's phase-shifting technology. Jim